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TDA7333

This interface consists of three lines: a serial data line (SDA), a bit clock (SCL), and a slave address select (SA).

The interface is capable of operating in fast mode (up to 400kbits/s) but also at lower rates (<100kbits/s).

Data transfers follow the format shown in Fig.8 . After the START condition (S), a slave address is sent. The

address is 7 bits long followed by an eighth bit which is a data direction bit (R/_W).

A ’zero’ indicates a transmission (WRITE), a ’one’ indicates a request for data (READ).

The slave address of the chip is set to 001000S, where S is the least significant bit of the slave address set

externally via the pin SA_DATAOUT. This allows to choose between two addresses in case of conflict with an-

other device of the radio set.

Each byte has to be followed by an acknowledge bit (SDA low).

Data is transfered with the most significant (MSB) bit first.

A data transfer is always terminated by a stop condition (P) generated by the master.

8.1 Write transfer

S

P

1-7

8

91-7

8

9

1-7

8

9

SDA

SCL

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK/ACK

S

S lave address

rd s_ int

A

A

A

sinc4reg

A

P

W

te streg

r d s_ b d _c trl

from master to slave

from slave to master

W = write mode

Slave address = 001000S ( where S is the level of the pin

SA_DATAOUT)

A = acknowledge bit

P = stop condition

S = start condition

A

S

SDA

SCL

START

CONDITION

WACK

rds_int[7:0]

rds_bd_ctrl[7:0]

P

STOP

CONDITION

ACK

ACK

SA

0

SLAVE ADDRESS