TDA7333

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Figure 18. read out RDS data and related flags, no update of rds_int and rds_bd_ctrl registers

Figure 19. write rds_int registers in spi mode,reading 1 register

The content of the rds registers is clocked out on DATAOUT pin in the following order:

rds_int[7:0], rds_qu[7:0], rds_corrp[7:0], rds_bd_l[7:0], rds_bd_h[7:0], rds_ctrl[7:0], sinc4reg[7:0], testreg[7:0]

For the meaning of the single bits please refer to the pages 13 to 15 .

Note : After 40 bit clocks the whole RDS data and flags are clocked out.

9

Application Notes

A typical rds data transfer could work like this:

1. The micro sets the interrupt source to “RDS block” interrupt by setting itsrc[2:0] to 001.

2. The micro continuously checks the rds_int[7:0] bits for the first interrupt ( rds_int[0] goes high). If

there is no interrupt it stops the transfer after these 8 bits. No update of the rds_int[7:0] is per-

formed.

3. Once there is an interrupt detected the micro will also clock out all the other RDS bits (rds_qu[7:0],

rds_corrp[7:0], rds_bd_h[7:0], rds_bd_l[7:0]).

4. The next interrupt can not be expected before 22ms.

The above example is working by polling the rds_int[0] bit. An easier and better application is possible by

checking the RDS interrupt pin INTN ( see below ) and starting the transfer only when this interrupt is

present.

The output pin INTN acts as an interrupt pin. The source of interrupt is programmable through the register

rds_int ( cf page 11), the value on the pin is the inverted value of the bit rds_int[0] ( i.e this interrupt pin is active

low). With the help of this pin an interrupt driven request of the rds data is possible (The external processor only

starts the transfer if an interrupt is active).

CSN

DATAIN

DATAOUT

CLK

rds_int[7:0]

rds_qu[7:0]

rds_corrp[7:0]

rds_bd_h[7:0]

rds_bd_l[7:0]

{0,x,x,x,x,x,x,x}

CSN

DATAIN

DATAOUT

CLK

rds_int[7:0]

{1,rds_int[6:0]}