ATA5811 datasheet(49/90 Pages) ATMEL

49 / 90 page

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

To save current it is recommended CLK and V

VSOUT be disabled during RX polling

mode. I

P does not include the current of the Microcontroller_Interface IVSINT and the cur-

rent of an external device connected to pin VSOUT (e.g., microcontroller). If CLK

and/or VSOUT is enabled during RX polling mode the current consumption is calculated

as follows:

During T

Sleep, TStartup_PLL and TStartup_Sig_Proc the transceiver is not sensitive to a transmit-

ter signal. To guarantee the reception of a transmitted command the transmitter

must start the telegram with an adequate preburst. The required length of the

preburst T

Preburst depends on the polling parameters TSleep, TStartup_PLL, TStartup_Sig_Proc

and T

Bit-check. Thus, TBit-check depends on the actual bit rate and the number of bits

Bit-check) to be tested

Sleep Mode

The length of period T

Sleep is defined by the 5-bit word sleep in control register 4, the

extension factor X

Sleep defined by the bit XSleep in control register 4 and the basic clock

cycle T

DCLK. It is calculated to be:

In US and European applications, the maximum value of T

Sleep is about 38 ms if XSleep is

set to 1 (which is done by setting the bit XSleep in control register 4 to 0). The time res-

olution is about 1.2 ms in that case. The sleep time can be extended to about 300 ms by

setting X

Sleep to 8 (which is done by setting XSleep in control register 4 to 1), the time

resolution is then about 9.6 ms.

Start-up Mode

During T

Startup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal pro-

cessing circuit starts up (T

Startup_Sig_Proc). After the start-up time all circuits are in stable

condition and ready to receive.

S_Poll

VSINT

EXT

Preburst

Sleep

Startup_PLL

Startup_Sig_Proc

Bit_check

≥

Sleep

1024

DCLK

Sleep

ATA5811 Datasheet(PDF) 49 Page - ATMEL Corporation

ATA5811 Datasheet(HTML) 49 Page - ATMEL Corporation

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