AD7714YN datasheet(32/41 Pages) AD

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AD7714

REV. C

–31–

The 68HC11 is configured in the master mode with its CPOL

bit set to a logic zero and its CPHA bit set to a logic one. When

the 68HC11 is configured like this, its SCLK line idles low

between data transfers. Therefore, the POL input of the AD7714

should be hard-wired low. For systems where it is preferable

that the SCLK idle high, the CPOL bit of the 68HC11 should

be set to a logic 1 and the POL input of the AD7714 should be

hard-wired to a logic high.

AD7714

DATA OUT

SCLK

SYNC

68HC11

DVDD

RESET

DATA IN

POL

SCK

MISO

MOSI

DVDD

Figure 9. AD7714 to 68HC11 Interface

The AD7714 is not capable of full duplex operation. If the

AD7714 is configured for a write operation, no data appears on

the DATA OUT lines even when the SCLK input is active.

Similarly, if the AD7714 is configured for a read operation, data

presented to the part on the DATA IN line is ignored even

when SCLK is active.

Coding for an interface between the 68HC11 and the AD7714

is given in Table XV. In this example, the

DRDY output line of

the AD7714 is connected to the PC0 port bit of the 68HC11

and is polled to determine its status.

AD7714 to 8051 Interface

An interface circuit between the AD7714 and the 8XC51 mi-

crocontroller is shown in Figure 10. The diagram shows the

minimum number of interface connections with

CS on the

AD7714 hard-wired low. In the case of the 8XC51 interface the

minimum number of interconnects is just two. In this scheme,

the

DRDY bit of the Communications Register is monitored to

determine when the Data Register is updated. The alternative

scheme, which increases the number of interface lines to three,

is to monitor the

DRDY output line from the AD7714. The

monitoring of the

DRDY line can be done in two ways. First,

DRDY can be connected to one of the 8XC51’s port bits (such

as P1.0) which is configured as an input. This port bit is then

polled to determine the status of

DRDY. The second scheme is

to use an interrupt driven system in which case, the

DRDY

output is connected to the

INT1 input of the 8XC51. For

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7714’s flexible serial interface allows for easy interface

to most microcomputers and microprocessors. The flowchart of

Figure 8 outlines the sequence which should be followed when

interfacing a microcontroller or microprocessor to the AD7714.

Figures 9, 10 and 11 show some typical interface circuits.

The serial interface on the AD7714 has the capability of operat-

ing from just three wires and is compatible with SPI interface

protocols. The three-wire operation makes the part ideal for

isolated systems where minimizing the number of interface lines

minimizes the number of opto-isolators required in the system.

The rise and fall times of the digital inputs to the AD7714

(especially the SCLK input) should be no longer than 1

µs.

Most of the registers on the AD7714 are 8-bit registers which

facilitates easy interfacing to the 8-bit serial ports of microcon-

trollers. Some of the registers on the part are up to 24 bits, but

data transfers to these 24-bit registers can consist of a full 24-bit

transfer or three 8-bit transfers to the serial port of the micro-

controller. DSP processors and microprocessors generally trans-

fer 16 bits of data in a serial data operation. Some of these

processors, such as the ADSP-2105, have the facility to program

the amount of cycles in a serial transfer. This allows the user to

tailor the number of bits in any transfer to match the register

length of the required register in the AD7714.

Even though some of the registers on the AD7714 are only eight

bits in length, communicating with two of these registers in

successive write operations can be handled as a single 16-bit

data transfer if required. For example, if the Mode Register is to

be updated, the processor must first write to the Communica-

tions Register (saying that the next operation is a write to the

Mode Register) and then write eight bits to the Mode Register.

This can all be done in a single 16-bit transfer if required be-

cause once the eight serial clocks of the write operation to the

Communications Register have been completed the part imme-

diately sets itself up for a write operation to the Mode Register.

AD7714 to 68HC11 Interface

Figure 9 shows an interface between the AD7714 and the

68HC11 microcontroller. The diagram shows the minimum

(three-wire) interface with

CS on the AD7714 hard-wired low.

In this scheme, the

DRDY bit of the Communications Register

is monitored to determine when the Data Register is updated.

An alternative scheme, which increases the number of interface

lines to four, is to monitor the

DRDY output line from the

AD7714. The monitoring of the

DRDY line can be done in two

ways. First,

DRDY can be connected to one of the 68HC11’s

port bits (such as PC0) which is configured as an input. This

port bit is then polled to determine the status of

DRDY. The

second scheme is to use an interrupt driven system in which

case, the

DRDY output is connected to the IRQ input of the

68HC11. For interfaces which require control of the

CS input

on the AD7714, one of the port bits of the 68HC11 (such as

PC1), which is configured as an output, can be used to drive the

CS input.

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