AD7714YN datasheet(21/41 Pages) AD

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AD7714

REV. C

–20–

ANALOG INPUT

Analog Input Ranges

The AD7714 contains six analog input pins (labelled AIN1 to

AIN6) which can be configured as either three fully differential

input channels or five pseudo-differential input channels. Bits

CH0, CH1 and CH2 of the Communications Register configure

the analog input arrangement and the channel selection is as

outlined previously in Table VII. The input pairs (either differ-

ential or pseudo-differential) provide programmable-gain, input

channels which can handle either unipolar or bipolar input

signals. It should be noted that the bipolar input signals are

referenced to the respective AIN(–) input of the input pair.

In unbuffered mode, the common-mode range of these inputs is

from AGND to AVDD provided that the absolute value of the analog

input voltage lies between AGND – 30 mV and AVDD + 30 mV.

This means that in unbuffered mode the part can handle both

unipolar and bipolar input ranges for all gains. In buffered

mode, the analog inputs can handle much larger source imped-

ances, but the absolute input voltage range is restricted to be-

tween AGND + 50 mV to AVDD – 1.5 V which also places

restrictions on the common-mode range. This means that in

buffered mode there are some restrictions on the allowable gains

for bipolar input ranges. Care must be taken in setting up the

common-mode voltage and input voltage range so that the

above limits are not exceeded, otherwise there will be a degrada-

tion in linearity performance.

In unbuffered mode, the analog inputs look directly into the

7 pF input sampling capacitor, CSAMP. The dc input leakage

current in this unbuffered mode is 1 nA maximum. As a result,

the analog inputs see a dynamic load which is switched at the

input sample rate (see Figure 3). This sample rate depends on

master clock frequency and selected gain. CSAMP is charged to

AIN(+) and discharged to AIN(–) every input sample cycle.

The effective on-resistance of the switch, RSW, is typically 7 k

Ω.

CSAMP must be charged through RSW and through any external

source impedances every input sample cycle. Therefore, in unbuf-

fered mode, source impedances mean a longer charge time for

CSAMP and this may result in gain errors on the part. Table XII

shows the allowable external resistance/capacitance values, for

unbuffered mode, such that no gain error to the 16-bit level is

introduced on the part. Table XIII shows the allowable external

resistance/capacitance values, once again for unbuffered mode,

such that no gain error to the 20-bit level is introduced.

Table XII. External R, C Combination for No 16-Bit Gain

Error (Unbuffered Mode Only)

Gain

External Capacitance (pF)

100

500

1000

5000

368 k

Ω 90.6 kΩ 54.2 kΩ 14.6 kΩ 8.2 kΩ

2.2 k

Ω

177.2 k

Ω 44.2 kΩ 26.4 kΩ 7.2 kΩ

4 k

Ω

1.12 k

Ω

82.8 k

Ω 21.2 kΩ 12.6 kΩ 3.4 kΩ

1.94 k

Ω 540 Ω

8–128

35.2 k

Ω 9.6 kΩ

5.8 k

Ω

1.58 k

Ω 880 Ω

240

Ω

Table XIII. External R, C Combination for No 20-Bit Gain

Error (Unbuffered Mode Only)

Gain

External Capacitance (pF)

100

500

1000

5000

290 k

Ω

69 k

Ω

40.8 k

Ω 10.4 kΩ 5.6 kΩ 1.4 kΩ

141 k

Ω

33.8 k

Ω 20 kΩ

5 k

Ω

2.8 k

Ω 700 Ω

63.6 k

Ω 16 kΩ

9.6 k

Ω

2.4 k

Ω

1.34 k

Ω 340 Ω

8–128

26.8 k

Ω 7.2 kΩ

4.4 k

Ω

1.1 k

Ω

600

Ω

160

Ω

In buffered mode, the analog inputs look into the high impedance

inputs stage of the on-chip buffer amplifier. CSAMP is charged via

this buffer amplifier such that source impedances do not affect

the charging of CSAMP. This buffer amplifier has an offset leak-

age current of 1 nA. In this buffered mode, large source imped-

ances result in a dc offset voltage developed across the source

impedance but not in a gain error.

Input Sample Rate

The modulator sample frequency for the AD7714 remains at

fCLK IN/128 (19.2 kHz @ fCLK IN = 2.4576 MHz) regardless of

the selected gain. However, gains greater than 1 are achieved

by a combination of multiple input samples per modulator cycle

and a scaling of the ratio of reference capacitor to input capaci-

tor. As a result of the multiple sampling, the input sample rate

of the device varies with the selected gain (see Table XIV). In

buffered mode, the input is buffered before the input sampling

capacitor. In unbuffered mode, where the analog input looks

directly into the sampling capacitor, the effective input imped-

ance is 1/CSAMP × fS where CSAMP is the input sampling capaci-

tance and fS is the input sample rate.

RSW (7k

TYP)

HIGH

IMPEDANCE

>1G

CSAMP

(7pF )

VBIAS

SWITCHING FREQUENCY DEPENDS ON

fCLKIN AND SELECTED GAIN

AIN(+)

AIN(–)

Figure 3. Unbuffered Analog Input Structure

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