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ADN2811 Datasheet(PDF) 8 Page - Analog Devices

Part # ADN2811
Description  OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
PDF  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADN2811 Datasheet(HTML) 8 Page - Analog Devices

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REV. A
–8–
ADN2811
JITTER SPECIFICATIONS
The ADN2811 CDR is designed to achieve the best bit-error-rate
(BER) performance and has exceeded the jitter generation, trans-
fer, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions measured in UI (unit intervals),
where 1 UI = 1 bit period. Jitter on the input data can cause
dynamic phase errors on the recovered clock sampling edge.
Jitter on the recovered clock causes jitter on the retimed data.
The following section briefly summarizes the specifications of
the jitter generation, transfer, and tolerance in accordance with
the Telcordia document (GR-253-CORE, Issue 3, September
2000) for the optical interface at the equipment level and the
ADN2811 performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter has
a 12 kHz high-pass cutoff frequency with a roll-off of 20 dB/
decade and a low-pass cutoff frequency of at least 20 MHz. The
jitter generated should be less than 0.01 UI rms and less
than 0.1 UI p-p.
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the fre-
quency. This parameter measures the limited amount of jitter
on an input signal that can be transferred to the output signal
(see Figure 7).
SLOPE = –20dB/DECADE
JITTER FREQUENCY – kHz
0.1
fC
ACCEPTABLE
RANGE
Figure 7. Jitter Transfer Curve
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal that causes a
1 dB power penalty. This is a stress test that is intended to
ensure no additional penalty is incurred under the operating
conditions (see Figure 8). Figure 9 shows the typical OC-48
jitter tolerance performance of the ADN2811.
SLOPE = –20dB/DECADE
f0
f1
f2
f3
f4
JITTER FREQUENCY – Hz
15
1.5
0.15
Figure 8. SONET Jitter Tolerance Mask
MODULATION FREQUENCY – Hz
1.00E+01
1.00E+03
1.00E+05
1.00E+07
1.00E+02
1.00E+01
1.00E–01
1.00E+00
1.00E+02
1.00E+04
1.00E+06
1.00E+00
ADN2811
OC-48 SONET MASK
Figure 9. OC-48 Jitter Tolerance Curve



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