4

4884A–AUDR–08/05

ATR4285

3.

Functional Description

The ATR4285 is controlled via the 2-wire bus. One module-address byte, two subaddress bytes,

and five data bytes enable programming.

The module address contains a programmable address bit A1, which (along with address select

input AS, pin 4) enables the operation of two ATR4285 devices in one system. If bit A1 is identi-

cal with the status of the address select input AS, the chip is selected.

The subaddress determines which of the data bytes is transmitted first. If the subaddress of the

R-divider is transmitted, the sequence of the next data bytes is DB 0 (status), DB 1 and DB 2. If

the subaddress of the N-divider is transmitted, the sequence of the next data bytes is DB 3 and

DB 4. The bit organization of the module address, subaddress and data bytes is shown in Table

“Bit Organization” on page 9.

Each transmission on the bus begins with the "START" condition and must be ended by the

"STOP" condition (see Table “Transmission Protocol” on page 9).

The integrated circuit ATR4285 has two separate inputs for the AM and FM oscillators. Pre-

amplified AM and FM signals are fed to the 16-bit N-divider via the AM/FM switch. The AM/FM

switch is software controlled. Tuning steps can be selected by the 16-bit R-divider.

Furthermore, the device provides a digital memory phase detector and two separate current

sources for AM and FM amplifiers (charge pump) as given in the Table “Electrical Characteris-

tics” on page 5. The separate current sources (charge pumps) allow independent gain

adjustment, providing high current for high-speed tuning and low current for stable tuning.