XRT83L30 datasheet(2/78 Pages) EXAR

2 / 78 page

XRT83L30

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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.0

PRELIMINARY

FEATURES

• Fully integrated single-channel long-haul and short-

haul transceiver for E1,T1 or J1 applications.

• Adaptive Receive Equalizer for cable attenuation of

up to 45dB for T1 and 43dB for E1.

• Programmable Transmit Pulse Shaper for E1,T1 or

J1 short-haul interfaces.

• Five fixed transmit pulse settings for T1 short-haul

applications plus a fully programmable waveform

generator for transmit output pulse shaping.

• Programmable Transmit Line Build-Outs (LBO) for

T1 long-haul application from 0dB to -22.5dB in

three 7.5dB steps.

• Tri-State transmit output and receive input capabil-

ity for redundancy applications

• Selectable receiver sensitivity from 0 to 36dB or 0

to 45dB cable loss for T1 @772kHz and 0 to 43dB

for E1 @1024kHz.

• High receiver interference immunity

• Receive monitor mode handles 0 to 29dB resistive

attenuation along with 0 to 6dB of cable attenuation

for both T1 and E1 modes.

• Supports 75

Ω and 120Ω (E1), 100Ω (T1) and 110Ω

(J1) applications.

• Internal and external impedance matching for

Ω,100Ω, 110Ω and 120Ω.

• Transmit return loss meets or exceeds ETSI 300

166 standard

• On-chip digital clock recovery circuit for high input

jitter tolerance

• Crystal-less digital jitter attenuator with 32-bit or 64-

bit FIFO Selectable either in transmit or receive

path

• On-chip frequency multiplier generates T1 or E1

Master clocks from variety of external clock sources

• On-chip transmit short-circuit protection and limit-

ing, and driver fail monitor output (DMO)

• Receive loss of signal (RLOS) output

• On-chip HDB3/B8ZS/AMI encoder/decoder

• QRSS pattern generation and detection for testing

and monitoring

• Error and Bipolar Violation Insertion and Detection

• Receiver Line Attenuation Indication Output in 1dB

steps

• Network Loop-Code Detection for automatic Loop-

Back Activation/Deactivation

• Transmit All Ones (TAOS) and In-Band Network

Loop Up and Down code generators

• Supports Analog, Remote, Digital and Dual Loop-

Back Modes

• Meets or exceeds T1 and E1 short-haul and long-

haul network access specifications in ITU G.703,

FIGURE 2. BLOCK DIAGRAM OF THE XRT83L30 T1/E1/J1 LIU (HARDWARE MODE)

HW/HOST

GAUGE

JASEL1

JASEL0

RXTSEL

TXTSEL

TERSEL1

TERSEL0

RXRES1

RXRES0

ICT

MCLKE1

MCLKT1

CLKSEL[2:0]

TXTEST[0:2]

INSBPV

TPOS / TDATA

TNEG / CODES

TCLK

QRPD

RCLK

RNEG / LCV

RPOS / RDATA

NLCD

RLOS

RTIP

RRING

MASTER CLOCK SYNTHESIZER

QRSS

PATTERN

GENERATOR

DMO

TTIP

TRING

TXON

HDB3/

B8ZS

ENCODER

TX/RX JITTER

ATTENUATOR

TIMING

CONTROL

TX FILTER

& PULSE

SHAPER

LINE

DRIVER

LOCAL

ANALOG

LOOPBACK

REMOTE

LOOPBACK

DIGITAL

LOOPBACK

HDB3/

B8ZS

DECODER

TX/RX JITTER

ATTENUATOR

TIMING &

DATA

RECOVERY

PEAK

DETECTOR

& SLICER

QRSS

DETECTOR

NETWORK

LOOP

DETECTOR

EQUALIZER

CONTROL

AIS

DETECTOR

LOS

DETECTOR

LBO[3:0]

LOOPBACK

ENABLE

NLCD ENABLE

QRSS ENABLE

HARWARE CONTROL

TEST

JABW

TRATIO

SR/DR

EQC[4:0]

TCLKE

RCLKE

RXMUTE

ATAOS

DRIVE

MONITOR

DFM

MCLKOUT

LOOP1

LOOP0

AISD

RESET

TAOS

ENABLE

XRT83L30 Datasheet(PDF) 2 Page - Exar Corporation

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