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SWITCHING CHARACTERISTICS

STATE TRANSITION LATENCY SPECIFICATIONS

CDCF5801

SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004

JITTER SPECIFICATION (continued)

over recommended free-air temperature range and V

TEST CONDITIONS

PARAMETER

TYP (ps)

MAX (ps)

REFCLK

CLKOUT

MULT[0:1] P[0:2]

NOTES

(MHz)

(MHz)

Period rms (1-sigma jitter, full

25

200

10

011

4

11

frequency band)

Period p-p

20

48

Cycle to cycle +

16

45

Cycle to cycle -

16

45

Period rms (1-sigma jitter, full

25

100

10

010

4

11

frequency band)

Period p-p

22

55

Cycle to cycle +

15

45

Cycle to cycle -

15

45

Period rms (1-sigma jitter, full

70

280

11

011

4

11

Phase

frequency band)

aligner

not running

Period p-p

18

48

(LEADLAG

Cycle to cycle +

15

45

= 0,

DLYCTRL =

Cycle to cycle -

15

45

0). All typi-

Period rms (1-sigma jitter, full

25

50

10

001

6

16

cal

frequency band)

values are

at

Period p-p

34

75

VDD = 3.3

Cycle to cycle +

20

65

25

°C.

Cycle to cycle -

20

65

Period rms (1-sigma jitter, full

78

156

11

010

3

11

frequency band)

Period p-p

15

44

Cycle to cycle +

13

40

Cycle to cycle -

13

40

Period rms (1-sigma jitter, full

62.5

125

00

011

6

20

frequency band)

Period p-p

35

80

Cycle to cycle +

25

75

Cycle to cycle -

25

75

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output duty cycle over 1000 cycles

See Figure 3

42%

58%

Output rise and fall times (measured at 20%-80% of output voltage

See Figure 5

150

250

350

ps

TEST

PARAMETER

FROM

TO

MIN

TYP

MAX

UNIT

CONDITION

Delay time, PWRDNB

↑ to CLKOUT /

3

CLKOUTB settled

Power down

Normal

See Figure 6

ms

Delay time, PWRDNB

↑ to internal PLL

3

and clock are on and settled

9