CDCF5801 datasheet(10/17 Pages) TI

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PARAMETER MEASUREMENT INFORMATION

TESTING CONDITIONS

CLKOUT

10 pF

Ω

CLKOUTB

VCM

CLKOUT

CLKOUTB

tCYCLE(i)

Cycle-to-Cycle Jitter (t(jitter)) = | tCYCLE(i) - tCYCLE(i+1) | over 1000 consecutive cycles

tCYCLE(i+1)

CDCF5801

SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004

STATE TRANSITION LATENCY SPECIFICATIONS (continued)

TEST

PARAMETER

FROM

MIN

TYP

MAX

UNIT

CONDITION

Delay time, power up to CLKOUT

output settled

t(VDDpowerup)

VDD

Normal

See Figure 6

Delay time, power up to internal PLL

and clock are on and settled

MULT0 and MULT1 change to

t(MULT)

Normal

See Figure 7

CLKOUT output resettled

STOPB

↑ to CLKOUT glitch-free clock

t(CLKON)

CLK stop

Normal

See Figure 8

edges

STOPB

↑ to CLKOUT output settled to

t(CLKSETL)

within 50 ps of the phase before

CLK stop

Normal

See Figure 8

cycles

STOPB was disabled

t(CLKOFF)

STOPB

↓ to CLKOUT output disabled

Normal

CLK stop

See Figure 8

Delay time, PWRDNB

↓ to the device in

t(powerdown)

Normal

Power down

See Figure 6

the power-down mode

Maximum time in CLKSTOP (STOPB =

t(STOP)

0) before reentering normal mode

STOPB

Normal

See Figure 8

100

µs

(STOPB = 1)

Minimum time in normal mode (STOPB

t(ON)

= 1) before reentering CLKSTOP

Normal

CLK stop

See Figure 8

100

(STOPB = 0)

Figure 1. Test Load and Voltage Definitions VOH, VOL, VO(STOP)

Figure 2. Cycle-to-Cycle Jitter

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