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ATECC508A Datasheet(PDF) 58 Page - Microchip Technology

Part # ATECC508A
Description  Cryptographic Co-processor with Secure Hardware-Based Key Storage
PDF  109 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ATECC508A Datasheet(HTML) 58 Page - Microchip Technology

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Command
Opcode Description
Typ. Exec.
Time(1)
Max. Exec.
Time(2)
Unit
SHA
0x47
Computes a SHA-256 or HMAC digest for general
purpose use by the system.
7
9
ms
UpdateExtra
0x20
Update bytes 84 or 85 within the Configuration zone after
the Configuration zone is locked.
8
10
ms
Verify
0x45
ECDSA verify calculation.
38
58
ms
Write
0x12
Write 4 or 32 bytes to the device, with or without
authentication and encryption.
7
26
ms
Note: 
1.
Typical execution times are representative of the duration to execute the command assuming no
error conditions, fastest mode setting, and favorable environmental conditions. For best
performance, delay for this interval and then start polling to determine actual command completion.
2.
Maximum execution times are representative of the longest duration of a successful command
execution under the worst case statistical and environmental conditions. Some internal modes,
such as limited use and others will cause the delays to be as much as 50 ms longer. In most but not
all cases, failing commands will return relatively quickly, often well before the typical execution time.
9.1.4
Address Encoding
The Read and Write commands include a single 16 bit address in Param2, which indicates the memory
location to be accessed. In all cases, data is accessed on 4 byte word boundaries. The word address can
be created by taking the byte address and dropping the least significant two bits.
The Read and Write commands support either 4 or 32 byte accesses. When 32 bytes are being
accessed, the offset (i.e. the least significant three bits of the word address) must be present in the
parameter, but their value in the parameter is ignored, and the operation proceeds assuming they are
zero (i.e. all 32 byte accesses are block aligned).
Table 9-5. Address Encoding for Config and OTP Zones (Param2)
Zone
Byte 1
Byte 0
Unused
Unused
Block
Offset
Config
Bits 7-0
Bits 7-5
Bits 4-3
Bits 2-0
OTP
Bits 7-0
Bits 7-4
Bit 3
Bits 2-0
Table 9-6. Address Encoding for Data Zone (Param2)
Zone
Byte 1
Byte 0
Unused
Block
Unused
Slot
Offset
Data Slots 0 – 7
Bits 7-1
Bit 0
Bit 7
Bits 6-3
Bits 2-0
Data Slot 8
Bits 7-4
Bits 3-0
Bit 7
Bits 6-3
Bits 2-0
Data Slots 9 – 15
Bits 7-2
Bits 1-0
Bit 7
Bits 6-3
Bits 2-0
Within each zone, there are various access restrictions as noted in the table below:
ATECC508A
Security Commands
© 2017 Microchip Technology Inc.
Datasheet Complete
DS20005927A-page 58



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