2

Integrated

Circuit

Systems, Inc.

ICS952802

Advance Information

0731—09/18/02

The ICS952802 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zero

delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks

signals for such a system.

The ICS952802 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the

first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the

use of a serially programmable I

output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each

individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting

under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

General Description

Block Diagram

CPUCLK8T (1:0)

AGPCLK (1:0)

PCICLK (8,6:0)

PCICLKF (1:0)

RESET#

CPUCLK8C (1:0)

PLL2

Frequency

Dividers

Programmable

Spread

PLL1

Programmable

Frequency

Dividers

STOP

Logic

12_48MHz

24_48MHz

X1

X2

XTAL

PD#

CPU_STOP#

PCI_STOP#

FS (4:0)

SEL24_48#

SEL12_48#

SELPCI_12#

Control

Logic

REF (2:0)

PCI7_12MHZ