3

Integrated

Circuit

Systems, Inc.

ICS952802

Advance Information

0731—09/18/02

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

2

*FS0/REF0

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

3

**FS1/REF1

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

4

**FS2/REF2

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

5

GNDREF

PWR

Ground pin for the REF outputs.

6

X1

IN

Crystal input,nominally 14.318MHz.

7

X2

OUT

Crystal output, nominally 14.318MHz.

8

GNDZ

PWR

Ground pin for the ZCLK outputs

9

ZCLK0

OUT

3.3V Hyperzip clock output.

10

ZCLK1

OUT

3.3V Hyperzip clock output.

11

VDDZ

PWR

Power supply for ZCLK clocks, nominal 3.3V

12

*PCI_STOP#/PCICLK8

I/O

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This

input is selected by IIC.

13

**FS3/PCICLK_F0

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

14

**FS4/PCICLK_F1

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

15

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

16

GNDPCI

PWR

Ground pin for the PCI outputs

17

PCICLK0

OUT

PCI clock output.

18

PCICLK1

OUT

PCI clock output.

19

PCICLK2

OUT

PCI clock output.

20

PCICLK3

OUT

PCI clock output.

21

PCICLK4

OUT

PCI clock output.

22

PCICLK5

OUT

PCI clock output.

23

GNDPCI

PWR

Ground pin for the PCI outputs

24

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

25

PCICLK6/SEL_Reset#*

I/O

PCI clock output / Latch input pin to select pin 48 function; 0 = Reset#. 1 = CPU_Stop#

26

PCICLK7/12MHz/SELPCI_12#**

I/O

PCICLK/12MHz clock output / Latched select input for PCI/12MHz output. 0 = 12MHz,

1 = PCICLK.

27

SDATA

I/O

Data pin for I2C circuitry 5V tolerant

28

GND48

PWR

Ground pin for the 48MHz outputs

29

24_48MHz/SEL24_48#*~

I/O

24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =

24MHz.

30

12_48MHz/SEL12_48#**

I/O

12/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =

12MHz.

31

AVDD48

PWR

Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V

32

SCLK

IN

Clock pin of I2C circuitry 5V tolerant

33

VDDAGP

PWR

Power supply for AGP clocks, nominal 3.3V

34

AGPCLK1

OUT

AGP clock output

35

AGPCLK0

OUT

AGP clock output

36

GNDAGP

PWR

Ground pin for the AGP outputs

37

PD#*

IN

Asynchronous active low input pin used to power down the device into a low power

state. The internal clocks are disabled and the VCO and the crystal are stopped. The

latency of the power down will not be greater than 3ms.

38

AVDD

PWR

3.3V Analog Power pin for Core PLL

39

AGND

PWR

Analog Ground pin for Core PLL

40

GNDCPU

PWR

Ground pin for the CPU outputs

41

CPUCLK8C0

OUT

"Complementary" clocks of differential 3.3V push-pull K8 pair.

42

CPUCLK8T0

OUT

"True" clocks of differential 3.3V push-pull K8 pair.

43

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

44

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

45

CPUCLK8C1

OUT

"Complementary" clocks of differential 3.3V push-pull K8 pair.

46

CPUCLK8T1

OUT

"True" clocks of differential 3.3V push-pull K8 pair.

47

GNDCPU

PWR

Ground pin for the CPU outputs

48

CPU_STOP#/Reset#*

I/O

Slectable real time CPU_Stop# (Input) or Reset# (Output)

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 1.5X Drive Strength