light filter that modulates light transmitted from the back to

the front of a display. A pixel’s bottom plate lies on the

backside of a display where a light source is applied, and the

top plate lies on the front, facing the viewer. On a Twisted

Neumatic (TN) display, which is typical of most TFT displays,

a pixel transmits the greatest amount of light when V

increases with either a positive or negative polarity. In short,

an LCD pixel can be thought of as a capacitor, through

which, a controlled amount of light is transmitted by varying

V

Figure 2 is a simplified block diagram of a TFT display,

showing how individual pixels are connected to the row,

column, and V

pacitor with an NMOS transistor connected to its top plate.

Pixels in a TFT panel are arranged in rows and columns.

Row lines are connected to the NMOS gates, and column

lines to the NMOS sources. The back plate of every pixel is

connected to a common voltage called V

ness is controlled by voltage applied to the top plates, and

the Column Drivers supply this voltage via the column lines.

Column Drivers ‘write’ this voltage to the pixels one row at a

time, and this is accomplished by having the Row Drivers

select an individual row of pixels when their voltage levels

are transmitted by the Column Drivers. The Row Drivers

sequentially apply a large positive pulse (typically 25V to

35V) to each row line. This turns-on NMOS transistors con-

nected to an individual row, allowing voltages from the col-

umn lines to be transmitted to the pixels.

V

The V

the pixels in a TFT panel. V

lies in the middle of the column drivers’ output voltage range.

As a result, when the column drivers write to a row of pixels,

they apply voltages that are either positive or negative with

respect to V

each time its row is selected. This allows the column drivers

to apply an alternating voltage to the pixels rather than a DC

signal, which can ‘burn’ a pattern into an LCD display.

When column drivers write to the pixels, current pulses are

injected onto the V

ing stray capacitance between V

(see Figure 2), which ranges typically from 16pF to 33pF per

column. Pixel capacitance contributes very little to these

pulses because only one pixel at a time is connected to a

column, and the capacitance of a single pixel is on the order

of only 0.5pF. Each column line has a significant amount of

series resistance (typically 2k

Ω to 40kΩ), so the stray ca-

pacitance is distributed along the entire length of a column.

This can be modeled by the multi-segment RC network

shown in Figure 3. The total capacitance between V

the column lines can range from 25nF to 100nF, and charg-

ing this capacitance can result in positive or negative current

pulses of 100mA, or more. In addition, a similar distributed

capacitance of approximately the same value exists be-

tween V

load is the sum of these distributed RC networks with a total

capacitance of 50nF to 200nF, and this load can modeled

like the circuit in Figure 3.

AV

source and sink current into a large capacitive load. To

simplify the analysis of this driver, the distributed RC network

of Figure 3 has been reduced to a single RC load in Figure

4. This load places a large capacitance on the V

output, resulting in an additional pole in the op amp’s feed-

back loop. However, the op amp remains stable because

C

pole. The range of C

Ω

to 100

Ω, so this zero will have a frequency in the range of

20059226

FIGURE 1. Individual LCD Pixel

20059227

FIGURE 2. TFT Display

20059228

FIGURE 3. Model of Impedance between V

Column Lines

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