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AD7710

REV. G

–17–

USING THE AD7710

SYSTEM DESIGN CONSIDERATIONS

The AD7710 operates differently from successive approxima-

tion ADCs or integrating ADCs. Because it samples the signal

continuously, like a tracking ADC, there is no need for a start

convert command. The output register is updated at a rate

determined by the first notch of the filter, and the output can be

read at any time, either synchronously or asynchronously.

Clocking

The AD7710 requires a master clock input, which may be an

external TTL/CMOS compatible clock signal applied to the

MCLK IN pin with the MCLK OUT pin left unconnected.

Alternatively, a crystal of the correct frequency can be connected

between MCLK IN and MCLK OUT, in which case the clock

circuit will function as a crystal-controlled oscillator. For lower

clock frequencies, a ceramic resonator may be used instead of

the crystal. For these lower frequency oscillators, external

capacitors may be required on either the ceramic resonator or

on the crystal.

The input sampling frequency, the modulator sampling fre-

quency, the –3 dB frequency, the output update rate, and the

calibration time are all directly related to the master clock fre-

quency fCLK IN. Reducing the master clock frequency by a factor

of 2 will halve the above frequencies and update rate and will

double the calibration time.

The current drawn from the DVDD power supply is also directly

related to fCLK IN. Reducing fCLK IN by a factor of 2 will halve the

DVDD current but will not affect the current drawn from the

AVDD power supply.

System Synchronization

If multiple AD7710s are operated from a common master clock,

they can be synchronized to update their output registers simul-

taneously. A falling edge on the

SYNC input resets the filter and

places the AD7710 into a consistent, known state. A common

signal to the AD7710s’

SYNC inputs will synchronize their

operation. This would typically be done after each AD7710 has

performed its own calibration or has had calibration coefficients

loaded to it.

The

SYNC input can also be used to reset the digital filter in

systems where the turn-on time of the digital power supply

(DVDD) is very long. In such cases, the AD7710 will start oper-

ating internally before the DVDD line has reached its minimum

operating level, 4.75 V. With a low DVDD voltage, the

AD7710’s internal digital filter logic does not operate correctly.

Thus, the AD7710 may have clocked itself into an incorrect

operating condition by the time that DVDD has reached its cor-

rect level. The digital filter will be reset upon issue of a calibra-

tion command (whether it is self-calibration, system calibration,

or background calibration) to the AD7710. This ensures correct

operation of the AD7710. In systems where the power-on

default conditions of the AD7710 are acceptable, and no cali-

bration is performed after power-on, issuing a

SYNC pulse to

the AD7710 will reset the AD7710’s digital filter logic. An R, C

on the

SYNC line, with R, C time constant longer than the

DVDD power-on time, will perform the SYNC function.

Accuracy

Sigma-delta ADCs, like VFCs and other integrating ADCs, do

not contain any source of nonmonotonicity and inherently offer

no missing codes performance. The AD7710 achieves excellent

linearity by the use of high quality, on-chip silicon dioxide

capacitors, which have a very low capacitance/voltage coefficient.

The device also achieves low input drift through the use of chopper

stabilized techniques in its input stage. To ensure excellent perfor-

mance over time and temperature, the AD7710 uses digital

calibration techniques that minimize offset and gain error.

Autocalibration

Autocalibration on the AD7710 removes offset and gain errors

from the device. A calibration routine should be initiated on the

device whenever there is a change in the ambient operating

temperature or supply voltage. It should also be initiated if there

is a change in the selected gain, filter notch, or bipolar/unipolar

input range. However, if the AD7710 is in its background cali-

bration mode, these changes are all automatically taken care of

(after the settling time of the filter has been allowed for).

The AD7710 offers self-calibration, system calibration, and

background calibration facilities. For calibration to occur on the

selected channel, the on-chip microcontroller must record the

modulator output for two different input conditions. These are

zero-scale and full-scale points. With these readings, the micro-

controller can calculate the gain slope for the input to output

transfer function of the converter. Internally, the part works

with a resolution of 33 bits to determine its conversion result of

either 16 bits or 24 bits.

The AD7710 also provides the facility to write to the on-chip

calibration registers, and, in this manner, the span and offset for

the part can be adjusted by the user. The offset calibration regis-

ter contains a value that is subtracted from all conversion

results, while the full-scale calibration register contains a value

that is multiplied by all conversion results. The offset calibration

coefficient is subtracted from the result prior to the multiplica-

tion by the full-scale coefficient. In the first three modes out-

lined here, the

DRDY line indicates that calibration is complete

by going low. If

DRDY is low before (or goes low during) the

calibration command, it may take up to one modulator cycle

before

DRDY goes high to indicate that calibration is in

progress. Therefore,

DRDY should be ignored for up to one

modulator cycle after the last bit of the calibration command is

written to the control register.

Self-Calibration

In the self-calibration mode with a unipolar input range, the

zero-scale point used in determining the calibration coefficients

is with both inputs shorted (that is, AIN(+) = AIN(–) = VBIAS)

and the full-scale point is VREF. The zero-scale coefficient is

determined by converting an internal shorted inputs node. The

full-scale coefficient is determined from the span between this

shorted inputs conversion and a conversion on an internal VREF

node. The self-calibration mode is invoked by writing the appro-

priate values (0, 0, 1) to the MD2, MD1, and MD0 bits of the

control register. In this calibration mode, the shorted inputs

node is switched in to the modulator first and a conversion is

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