AD7710 datasheet(20/33 Pages) AD

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AD7710

REV. G

–19–

Span and Offset Limits

Whenever a system calibration mode is used, there are limits on

the amount of offset and span that can be accommodated. The

range of input span in both the unipolar and bipolar modes has

a minimum value of 0.8

× V

REF/GAIN and a maximum value of

2.1

× V

REF/GAIN.

The amount of offset that can be accommodated depends on

whether the unipolar or bipolar mode is being used. This offset

range is limited by the requirement that the positive full-scale

calibration limit is

≤ 1.05 × V

REF/GAIN. Therefore, the offset

range plus the span range cannot exceed 1.05

× VREF/GAIN. If

the span is at its minimum (0.8

× V

REF/GAIN), the maximum

the offset can be is (0.25

× V

REF/GAIN).

In bipolar mode, the system offset calibration range is again

restricted by the span range. The span range of the converter in

bipolar mode is equidistant around the voltage used for the

zero-scale point, thus the offset range plus half the span range

cannot exceed (1.05

× VREF/GAIN). If the span is set to 2 ×VREF/

GAIN, the offset span cannot move more than

±(0.05 × V

REF/

GAIN) before the endpoints of the transfer function exceed the

input overrange limits

±(1.05 × VREF/GAIN). If the span range

is set to the minimum

± (0.4 × V

REF/GAIN), the maximum

allowable offset range is

±(0.65 × V

REF/GAIN).

POWER-UP AND CALIBRATION

On power-up, the AD7710 performs an internal reset, which

sets the contents of the control register to a known state. How-

ever, to ensure correct calibration for the device, a calibration

routine should be performed after power-up.

The power dissipation and temperature drift of the AD7710

are low and no warm-up time is required before the initial

calibration is performed. However, if an external reference is

being used, this reference must have stabilized before calibration

is initiated.

Drift Considerations

The AD7710 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and dc

leakage currents at the sampling node are the primary sources of

offset voltage drift in the converter. The dc input leakage current is

essentially independent of the selected gain. Gain drift within the

converter depends primarily upon the temperature tracking of the

internal capacitors. It is not affected by leakage currents.

Measurement errors due to offset drift or gain drift can be elimi-

nated at any time by recalibrating the converter or by operating

the part in the background calibration mode. Using the system

calibration mode can also minimize offset and gain errors in the

signal conditioning circuitry. Integral and differential linearity

errors are not significantly affected by temperature changes.

POWER SUPPLIES AND GROUNDING

Because the analog inputs and reference input are differential,

most of the voltages in the analog modulator are common-mode

voltages. VBIAS provides the return path for most of the analog

currents flowing in the analog modulator. As a result, the VBIAS

input should be driven from a low impedance to minimize errors

due to charging/discharging impedances on this line. When the

internal reference is used as the reference source for the part,

AGND is the ground return for this reference voltage.

The analog and digital supplies to the AD7710 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The digital filter will

provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital supply (DVDD) must not exceed the analog positive

supply (AVDD) by more than 0.3 V in normal operation. If sepa-

rate analog and digital supplies are used, the recommended

decoupling scheme is shown in Figure 9. In systems where

AVDD = 5 V and DVDD = 5 V, it is recommended that AVDD

and DVDD are driven from the same 5 V supply, although

each supply should be decoupled separately as shown in Fig-

ure 9. It is preferable that the common supply is the system’s

analog 5 V supply.

It is also important that power is applied to the AD7710 before

signals at REF IN, AIN, or the logic input pins in order to avoid

excessive current. If separate supplies are used for the AD7710

and the system digital circuitry, then the AD7710 should be

powered up first. If it is not possible to guarantee this, then

current limiting resistors should be placed in series with the

logic inputs.

AD7710

0.1 F

10 F

ANALOG

SUPPLY

DIGITAL +5V

SUPPLY

AVDD

DVDD

Figure 9. Recommended Decoupling Scheme

DIGITAL INTERFACE

The AD7710’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7710 can access data from the output

serial write to the AD7710 can write data to the control register

or the calibration registers.

Two different modes of operation are available, optimized for

different types of interfaces where the AD7710 can act either as

master in the system (it provides the serial clock) or as slave (an

external serial clock can be provided to the AD7710). These

two modes, labeled self-clocking mode and external clocking

mode, are discussed in detail in the following sections.

Self-Clocking Mode

The AD7710 is configured for its self-clocking mode by tying

the MODE pin high. In this mode, the AD7710 provides the

serial clock signal used for the transfer of data to and from the

AD7710. This self-clocking mode can be used with processors

that allow an external device to clock their serial port including

most digital signal processors and microcontrollers such as the

68HC11 and 68HC05. It also allows easy interfacing to serial-

parallel conversion circuits in systems with parallel data commu-

nication, allowing interfacing to 74XX299 universal shift

registers without any additional decoding. In the case of shift

registers, the serial clock line should have a pull-down resistor

instead of the pull-up resistor shown in Figure 10 and Figure 11.

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