Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial

Interface

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13

Acknowledge Bit (ACK) and Not-

Acknowledge Bit (NACK)

Successful data transfers are acknowledged with an

acknowledge bit (ACK) or a not-acknowledge bit

(NACK). Both the master and the MAX5115/MAX5116

(slave) generate acknowledge bits. To generate an

acknowledge, the receiving device must pull SDA low

before the rising edge of the acknowledge-related

clock pulse (ninth pulse) and keep it low during the

high period of the clock pulse (Figure 7). To generate a

not acknowledge, the receiver allows SDA to be pulled

high before the rising edge of the acknowledge-related

clock pulse and leaves it high during the high period of

the clock pulse.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer happens if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the master should reattempt com-

munication at a later time.

Slave Address

A master initiates communication with a slave device

by issuing a START condition followed by a slave

address (Figure 8). The slave address consists of 7

address bits and a read/write bit (R/W). When idle, the

device continuously waits for a START condition fol-

lowed by its slave address. When the device recog-

nizes its slave address, it acquires the data byte and

executes the command. The first 3 bits (MSBs) of the

slave address have been factory programmed and are

the remaining 4 bits of the slave address. The least sig-

nificant bit (LSB) of the address byte (R/W) determines

whether the master is writing to or reading from the

MAX5115/MAX5116. (R/W = 0 selects a write condition.

R/W = 1 selects a read condition.) After receiving the

address, the MAX5115/MAX5116 (slave) issues an

acknowledge by pulling SDA low for one clock cycle.

SCL

SDA

STOP

START

SCL

SDA

ILLEGAL

STOP

START

ILLEGAL EARLY STOP CONDITION

LEGAL STOP CONDITION

Figure 6. Early STOP Conditions

18

9

ACKNOWLEDGE

NOT ACKNOWLEDGE

SCL

S

SDA

Figure 7. Acknowledge and Not-Acknowledge Bits

SCL

SDA

123

0

A3

1

0

89

45

67

A2

A1

A0

R/W

ACK

ACKNOWLEDGE

S

Figure 8. Slave Address Byte