AD5590BBCZ datasheet(13/45 Pages) AD

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AD5590

Rev. A | Page 12 of 44

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOUT14

IN5(+)

IN5(–)

OUT5

OUT6

V2–

IN6(–)

IN6(+)

IN7(+)

IN7(–)

OUT7

VIN12

VOUT10

IN4(+)

VIN11

VIN14

VREFA

VIN15

VREFIN2/

VREFOUT2

VOUT15

VOUT13

VOUT11

VOUT9

VIN10

VOUT8

IN4(–)

VIN13

VOUT12

DACGND

OUT4

V2+

VOUT1

LDAC

ADCVDD

ADIN

DACVDD

DDIN

ASYNC

ASCLK

DSYNC2

DSCLK

ADOUT

VDRIVE

CLR

DSYNC1

ADCGND

VIN1

DACGND

DACVDD

VIN0

VIN3

VOUT3

VOUT5

V1+

VIN2

VIN9

VOUT7

IN0(+)

VIN4

VIN6

VIN7

V1–

VIN5

VREFIN1/

VREFOUT1

VOUT6

VOUT4

VOUT2

VIN8

VOUT0

IN0(–)

OUT0

IN1(+)

IN1(–)

OUT1

OUT3

IN3(–)

IN3(+)

IN2(–)

IN2(+)

OUT2

Figure 5. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Description

ASYNC

Frame Synchronization Signal. Active low logic input. This input provides the dual function of

initiating ADC conversions and also frames the serial data transfer.

J11

VREFA

Reference Input for the ADC Block. An external reference must be applied to this input. The voltage

range for the external reference is 2.5 V ± 1% for specified performance.

ADCVDD

Power Supply Input for the ADC Block. The ADC can operate from 4.5 V to 5.25 V, and the supply

should be decoupled with a 10 µF in parallel with a 0.1 µF capacitor to ADCGND.

ADCGND

Ground Reference Point for the ADC Block. All ADC analog/digital input/output signals and any

external reference signal should be referred to this ADCGND voltage.

M4, L5, L3, L4, L2,

G2, K2, J2, B2, B3,

B11, L11, B12, L10,

K11, H11

VIN0 to

VIN15

Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are

multiplexed into the on-chip track and hold. The analog input channel to be converted is selected by

using the ADD3 through ADD0 address bits of the control register. The address bits in conjunction

with the SEQ and shadow bits allow the sequence register to be programmed. The input range for all

input channels can extend from 0 V to VREFA or 0 V to 2 × VREFA, as selected via the range bit in the

control register. Any unused input channels should be connected to GND to avoid noise pickup.

ADIN

ADC Data In. Logic input. Data to be written to the control register of the ADC is provided on this input and

is clocked into the register on the falling edge of ASCLK (see the Accessing the ADC Block section).

ADOUT

Data Out. Logic output. The conversion result from the ADC block is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the ASCLK input. The data stream consists

of four address bits indicating which channel the conversion result corresponds to, followed by the

12 bits of conversion data, which is provided MSB first. The output coding can be selected as straight

binary or twos complement via the coding bit in the control register.

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