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FS6127 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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FS6127 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 6 page ![]() XT February 1999 4 2.4.99 )6 9&;2 &ORFN*HQHUDWRU,& $GYDQFH ,QIRUPDWLRQ ,62 Table 5: DC Electrical Specifications Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Supply Current, Dynamic, with Loaded Outputs IDD fXTAL = 13.5MHz; CL = 10pF 20 mA Voltage Controlled Crystal Oscillator Crystal Resonator Frequency fXTAL Fundamental Mode 10 13.5 15 MHz Crystal Loading Capacitance CL(xtal) As seen by a crystal connected to XIN and XOUT (@ VXTUNE = 1.65V) 14 pF Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF VCXO Tuning Range fXTAL = 13.5MHz; CL = 14pF; CMOT = 25fF 300 ppm VCXO Tuning Characteristic Note: positive ∆F for positive ∆V 100 ppm/V Crystal Drive Level RXTAL=20 ohm; CL = 14pF 200 uW Clock Output (CLK) High-Level Output Source Current * IOH VO = 2.0V mA Low-Level Output Sink Current * IOL VO = 0.4V mA zOH VO = 0.1VDD; output driving high Output Impedance * zOL VO = 0.1VDD; output driving low Ω Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. mA Short Circuit Sink Current * IOSL VO = 5V; shorted for 30s, max. mA Table 6: AC Timing Specifications Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS Clock Outputs (CLKx) Duty Cycle * thi / tclk; Measured at VDD/2 45 55 % Jitter, Absolute Period (pk-pk) * tj(∆P) From rising edge to next rising edge at VDD/2, CL = 10pF 300 ps Jitter, RMS Long Term ( σ y( τ)) * tj(LT) From 0-500 µs at V DD/2, CL = 10pF compared to ideal clock source 150 ps Rise Time * tr VDD = 5V; VO = 0.5V to 4.5V; CL = 10pF ns Fall Time * tf VDD = 5V; VO = 4.5V to 0.5V; CL = 10pF ns Output Frequency Synthesis Error (unless otherwise noted in Frequency Table) 0 ppm VCXO Stabilization Time * tVCXOSTB From power valid 10 ms PLL Stabilization Time * tPLLSTB From VCXO stable 500 us |
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