SSD1850 datasheet(19/56 Pages) ETC

19 / 56 page

SSD1850/51 Series

Rev 1.2

01/2003

SOLOMON

MPU Serial 4-wire Interface

The serial interface consists of serial clock SCK, serial data SDA, D/ C and CS . Input to SDA is shifted

into a 8-bit shift register on every rising edge of SCK in the order of D7, D6,...D0. D/ C is sampled on every

eighth clock and the content in the shift register is written to the Display Data RAM or command register

in the same clock. No extra clock or command is required to end the transmission.

MPU Serial 3-wire Interface

Operation is similar to 4-wire serial interface except D/ C is not used. The Set Display Data Length

command is used to indicate that a specified number display data byte (1-256) is to be transmitted. Next

byte after the display data string is handled as a command.

It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the serial

communication, a hardware reset pulse at RES pin is required to initialize the chip for re-synchronization.

Modes of operation

6800 parallel

8080 parallel

Serial

Data Read

Yes

Data Write

Yes

Command Read

Status only

Command Write

Yes

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is

128 x 81 x 2 = 20736bits. Figure 5 is a description of the GDDRAM address map. For mechanical

flexibility, remapping on both Segment and Common outputs are provided respectively. For vertical

scrolling of display, an internal register storing the display start line can be set to control the portion of the

RAM data to be mapped to the display. Figure 5a and 5b show the cases in which the display start line

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