AD571

REV.

–8–

zero, blanking the previously active port at the same time. Sub-

sequently, this second device can be read by the microprocessor,

and so-forth. The status lines are wire-ored in 2 groups and

connected to the two remaining control pins. This allows a con-

version status check to be made after a convert command, if

necessary. The ADCs are divided into two groups to minimize

the loading effect of the internal pull-up resistors on the

DATA

READY buffers.

with the 2 control bits (which act as outputs), are used to con-

trol the 8 AD571s. When a control line is in the “1” or high

state, the ADC will be automatically blanked. That is, its out-

puts will be in the inactive open state. If a single control line is

switched low, its ADC will convert and the outputs will auto-

matically go active when the conversion is complete. The result

can then be read from the two peripheral ports; when the next

conversion is desired, a different control line can be switched to

B

OUTLINE DIMENSIONS

18

1

9

10

0.310 (7.87)

0.220 (5.59)

PIN 1

0.098 (2.49) MAX

0.005 (0.13) MIN

SEATING

PLANE

0.023 (0.58)

0.014 (0.36)

0.060 (1.52)

0.015 (0.38)

0.200 (5.08)

MAX

0.200 (5.08)

0.125 (3.18)

0.070 (1.78)

0.030 (0.76)

0.960 (24.38) MAX

0.100

(2.54)

BSC

0.150

(3.81)

MIN

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 16. 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-18)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD571JD

18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

D-18

AD571SD

18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

D-18

AD571SD/883B

18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

D-18

5962-8680202VA

18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

D-18

REVISION HISTORY

4/12—Rev. A to Rev. B

Changes to Temperature Coefficients Full-Scale Calibration

Parameter ...........................................................................................2

Changes to V+ Operating Current Parameter ..............................2

Updated Outline Dimensions..........................................................8

Added Ordering Guide and Revision History Section ................8

©2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D

10739-0-4/12(B)