Data Sheet

VSC7127/VSC7129

Family of Repeater/Retimer and Port

Bypass Circuits for Fibre Channel

G52298-0, Rev 4.3

Page 9

05/01/01

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Table 4: Pin Identification

Pin #

Name

Description

4, 3

41, 40

35, 34

28, 27

10, 9

I1+, I1-

I2+, I2-

I3+, I3-

I4+, I4-

I0+, I 0-

I1+/I1- is the serial input to PBC1.

I2+/I2- is the serial input to PBC2.

I3+/I3- is the serial input to PBC3.

I4+/I4- is the serial input to PBC4.

I0+/I0- is the serial input to PBC0.

15, 16,

17, 18

14, 22

SEL1, SEL2

SEL3, SEL4

SEL0, SEL5

INPUT - TTL.

Port Bypass MUX SELect lines. A HIGH selects Ix. A LOW selects the

output of the previous internal device.

7, 6

44, 43

38, 37

31, 30

24, 25

O1+, O1-

O2+, O2-

O3+, O3-

O4+, O4-

O0+, O0-

OUTPUT - Differential

O1+/O1- is the serial output from MUX1.

O2+/O2- is the serial output from PBC port 1.

O3+/O3- is the serial output from PBC port 2.

O4+/O4- is the serial output from PBC port 3.

O0+/O0- is the serial output from PBC port 4.

13

REFCLK

INPUT - TTL

106.25MHz REFerence CLocK for the internal Clock Multiplier PLL.

NOTE: A reference clock must be provided to the REFCLK pin in order for

the chip to power up in the right state

12

MODE

INPUT - TTL

(NOTE: Different for VSC7127T or VSC7127R)

In the VSC7127T, MODE configures the part as a Retimer if LOW or a

Repeater if HIGH. In the VSC7127R, MODE configures the parts as a

Repeater if LOW or a Retimer if HIGH. If unused, tie HIGH or LOW.

20 (VSC7127)

19 (VSC7129

SIGDET

OUTPUT - TTL:

SIGnal DETect output

23 (VSC7127)

22 (VSC7129)

TRST

INPUT - TTL:

(Internal Pull-up Resistor)

Test mode input. Pull HIGH or leave open for normal operation.

2

21 (VSC7127)

20 (VSC7129)

VDD

Digital Logic Power Supply

5

42

36

29

26

VDDP1

VDDP2

VDDP3

VDDP4

VDDP0

32

VDDA

Analog Power Supply

1, 8, 11, 33, 39

19 (VSC7127)

23 (VSC7129)

VSS

Ground