XR68C192IP datasheet(11/32 Pages) EXAR

11 / 32 page

XR68C92/192

Rev. P1.10

for the respective channel is negated. Data is trans-

ferred from the transmit holding register to the transmit

shift register when the shift register is idle or has

completed transmission of the previous character. The

transmitter ready conditions are then reasserted, pro-

viding one full character time of buffering. Characters

cannot be loaded into the transmit buffer while the

transmitter is disabled.

The transmitter converts the parallel data from the CPU

to a serial bit stream on the transmitter serial-data

output pin. It automatically sends a start bit followed by

the programmed number of data bits, an optional parity

bit, and the programmed number of stop bits. The least-

significant bit is sent first. Data is shifted out the

transmit serial data output pin on the falling edge of the

programmed clock source. After the transmission of the

stop bits, and a new character is not available in the

transmit holding register, the transmitter serial-data

output remains high and the transmitter-empty bit in the

status register (SRA and SRB) will be set to one.

Transmission resumes and the transmitter-empty bit is

cleared when the CPU loads a new character into the

transmit buffer. If the transmitter receives a disable

command, it will continue operating until the character

in the transmit shift register is completely sent out.

Other characters in the holding register are neither sent

nor discarded, but will be sent when the transmitter is

re-enabled. Users can program the transmitter to auto-

matically negate the request-to-send (RTS) output (al-

ternate function of OP0 and OP1) on completion of a

message transmission. If the transmitter is pro-

grammed to operate in this manner, the RTS output

must be manually asserted before each message is

transmitted. If OP0 (or OP1) is programmed in auto-

matic RTS mode, the RTS output will be automatically

negated when the transmitter is disabled and the

transmit-shift register and holding register are both

empty. In automatic RTS mode, a character in the

holding register is not held back by a disable, but no

more characters can be written to the holding register

after the transmitter is disabled.

If clear-to-send (CTS) operation is enabled, the CTS

input (alternate function of IP0 or IP1) must be low in

order for the character to be transmitted. If it goes high

in the middle of a transmission, the character in the shift

marking state until CTS again goes low. The transmitter

can also be forced to send a continuous low condition

by issuing a send-break command. The state of CTS is

ignored by the transmitter when it is set to send break.

A send break is deferred as long as the transmitter has

characters to send, but if normal character transmis-

sion is inhibited by CTS, the send-break will proceed.

The send-break must be terminated by a stop-break,

disable, or reset before normal character transmission

can resume.

The transmitter can be reset through a software com-

mand. If it is reset, operation ceases immediately and

must be enabled through the command register before

resuming operation. Reset also discards any character

in the holding register.

RECEIVER

The channel A and B receivers are enabled for data

reception through the respective channels command

low (mark-to-space) transition of a start bit on the

receiver serial-data input pin. If operating in 16X clock

mode, the serial input data is re-sampled on the next

7 clocks. If the receiver serial data is sampled high, the

start bit is invalid and the search for a valid start bit

begins again. If receiver serial data is still low, a valid

start bit is assumed and the receiver continues to

sample the input at one bit time intervals (at the

theoretical center of the bit) until the proper number of

data bits and the parity bit (if any) have been as-

sembled and one stop bit has been detected. Data on

the receiver serial data input pin is sampled on the

rising edge of the programmed clock source.

During this process, the least-significant bit is re-

ceived first. The data is then transferred to a receive

holding register (RHR) and the receiver-ready bit in

the status register (SRA or SRB) is set to one. This

condition can be programmed to generate an interrupt

request on the -INT output, an interrupt request for

channel A receiver on output pin( OP4), or an interrupt

request for channel B receiver on output pin (OP5). If

the character length is less than eight bits, the most

significant unused bits in the receive holding register

(RHR) are set to zero.

If the stop bit is sampled as a 1, the receiver will

immediately look for the next start bit. However, if the

stop bit is sampled as a 0, either a framing error or a

received break has occurred. If the stop bit is 0 and the

data and parity (if any) are not all zero, it is a framing

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