S9408P datasheet(2/10 Pages) SUMMIT

2 / 10 page

S9408

2015 2.2 8/2/00

SUMMIT MICROELECTRONICS, Inc.

The analog outputs of the S9408 can be programmed to

any one of 256 individual voltage steps. Each step value

is 1/256th of the voltage differential between VREFH and

VREFL of the respective DAC. Once programmed these

settings can be retained in nonvolatile memory during all

power conditions and will be automatically recalled upon

a power-up sequence. Each DAC can be independently

read without affecting the output voltage during the read

cycle. In addition, each output can be adjusted an unlim-

ited number of times without altering the value stored in

the nonvolatile memory.

DEVICE OPERATION

Analog Section

The S9804 is an 8-bit, voltage output digital-to-analog

converter (DAC). The DAC consists of a resistor network

that converts 8-bit digital inputs into equivalent analog

output voltages in proportion to the applied reference

voltage.

Reference inputs

The voltage differential between the VREFL and VREFH

inputs sets the full-scale output voltage for its respective

DAC. VREFL must be equal to or greater than ground

(positive voltage). VREFH must be greater (more positive)

than VREFL and less than or equal to VDD.

PINOUT and SIGNAL DEFINITION

Name

Function

1, 2

VREFH

Vreference High:

20, 19

VREFL < VREFH - VDD

3VDD

Power Supply Voltage

RDY/BSY# Ready/Busy: open drain output

indicating status of nonvolatile

write operations

CLK

Clock Input Pin: used for serial

data communication

CS#

Chip Select: When high deselects

the device and places it in a low

power mode

Data Input: serial data input pin

Data Output: serial data output pin

00/REG#

Power On Recall Option Input

GND

Power Supply Ground

11, 12

VREFL

Vreference Low:

13, 14

VREFH > VREFL • GND

15, 16

VOUT

DAC Output: buffered D to A

17, 18

converter output

Output Buffer Amplifiers

The voltage outputs are precision unity-gain followers that

slew up to 1V/µs. The outputs can swing from VREFL to

VREFH. With a 0V to 5V output transition the amplifier

outputs typically settle to 1LSB in 40µs.

DIGITAL INTERFACE

The S9408 employs a common 4-wire serial interface. It

is comprised of a Clock (CLK), Chip Select (CS#), Data In

(DI) and Data Out (DO). Data is clocked into the device on

the clock’s rising edge and out of the device on the clock’s

falling edge. Data is shifted in and out MSB first. DO only

becomes active after the device has been selected and

after a valid read command and address has been re-

ceived.

All data transfers are initiated after CS# goes low and a

logic ‘1’ is clocked into the device. This first data transfer

is the start bit and must precede all operations. Following

the start bit are two command bits used to specify which

of four commands to execute. The next two bits are the

address bits used to select one of the four DACs. The

action of the next eight clock cycles will be dependent

upon the command issued.

VREFH1

VREFH0

VDD

RDY/BSY#

CLK

CS#

00/REG#

GND

VREFH2

VREFH3

VOUT0

VOUT1

VOUT2

VOUT3

VREFL3

VREFL2

VREFL1

VREFL0

2015 T PCon 2.0

20-Pin PDIP

or 20-Pin SOIC

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