SI5381 datasheet(4/51 Pages) SILABS

4 / 51 page

Table of Contents

1. Feature List ................................ 2

2. Ordering Guide

.............................. 3

3. Functional Description............................ 6

3.1 Frequency Configuration .......................... 6

3.1.1 Si5381/82 4G/LTE Frequency Configuration

................. 6

3.1.2 Si5381/82 Configuration for Wireless Clock Generation .............. 7

3.1.3 DSPLL Loop Bandwidth ........................ 7

3.1.4 Fastlock .............................. 7

3.1.5 Modes of Operation .......................... 8

3.1.6 Initialization and Reset ......................... 8

3.1.7 Free-run Mode

........................... 8

3.1.8 Lock Acquisition ........................... 8

3.1.9 Locked Mode ............................ 8

3.1.10 Holdover Mode ........................... 9

3.2 External Reference (XA/XB) (Grade A Only)

...................10

3.3 Inputs (IN0, IN1, IN2, IN3) ..........................11

3.3.1 Input Configuration and Terminations ....................12

3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3) ..................12

3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3) .................13

3.3.4 Hitless Input Switching .........................13

3.3.5 Glitchless Input Switching ........................13

3.3.6 Zero Delay Mode (ZDM) ........................14

3.4 Fault Monitoring .............................15

3.4.1 Input LOS Detection..........................15

3.4.2 Reference LOS Detection ........................15

3.4.3 OOF Detection

...........................16

3.4.4 Precision OOF Monitor .........................16

3.4.5 Fast OOF Monitor ..........................16

3.4.6 LOL Detection............................17

3.4.7 Interrupt Pin INTRb ..........................18

3.5 Outputs ................................18

3.5.1 Output Crosspoint ..........................18

3.5.2 Output Signal Format .........................18

3.5.3 Output Terminations..........................19

3.5.4 Programmable Common Mode Voltage for Differential Outputs ...........19

3.5.5 LVCMOS Output Terminations ......................20

3.5.6 LVCMOS Output Impedance and Drive Strength Selection.............20

3.5.7 LVCMOS Output Signal Swing ......................20

3.5.8 LVCMOS Output Polarity ........................20

3.5.9 Output Enable/Disable .........................21

3.5.10 Output Disable During LOL .......................21

3.5.11 Output Disable During Reference LOS (XAXB, Internal Crystal)

..........21

3.5.12 Output Driver State When Disabled ....................21

3.5.13 Synchronous Enable/Disable Feature ...................21

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