3.5.9 Output Enable/Disable

The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held

high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually

disabled through register control.

3.5.10 Output Disable During LOL

By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option

to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.

3.5.11 Output Disable During Reference LOS (XAXB, Internal Crystal)

The internal oscillator circuit (OSC) in combination with the external XA/XB reference (Grade A) internal crystal (Grade E) provides a

critical function for the operation of the DSPLLs. In the event of a crystal failure, the device will assert an XAXB_LOS alarm. By default,

all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an

XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition. The internal oscillator circuit

(OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the DSPLLs.

3.5.12 Output Driver State When Disabled

The disabled state of an output driver is configurable as either disable low or disable high.

3.5.13 Synchronous Enable/Disable Feature

The output drivers provide a selectable synchronous enable/disable feature. Output drivers with this feature active will wait until a clock

period has completed before the driver is disabled or enabled. This prevents unwanted runt pulses from occurring when enabling or

disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete.

3.5.14 Output Divider (R) Synchronization

All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable

phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the reset bit will have the same result.

Asserting the sync register bit provides another method of realigning the R dividers without resetting the device.

3.6 Power Management

Unused inputs and output drivers can be powered down when unused. Consult the ClockBuilder Pro configuration utility for details.

3.6.1 Power Down Pin (PDNb)

A power down pin is provided to force the device in a low power mode. The device’s configuration will be maintained but no output

clocks will be generated. Most of the internal blocks will be shut down but device communication via the serial interface will still be

available. When the PDNb pin is pulled low the outputs will shut down without glitching (the clock’s complete period will be generated

before shutting down). When PDNb is released the device will start generating clocks without glitches. The device will generate free-

running clocks until each DSPLL has acquired lock to the selected input clock source.

3.7 In-Circuit Programming

The Si5381/82 is fully configurable using the serial interface (I2C or SPI). At power-up, the device downloads its default register values

from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-

erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-

ply voltages applied to its VDD and VDDA pins. The NVM is writable two times. Once a new configuration has been written to NVM, the

old configuration is no longer accessible. Refer to the Si5381/82 Family Reference Manual for a detailed procedure for writing registers

to NVM.

3.8 Serial Interface

Configuration and operation of the Si5381/82 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL

pin selects I2C or SPI operation. The Si5381/82 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL config-

uration bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit.

Si5381/82 Data Sheet

Functional Description

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