Si8450/51/52/55

Rev. 1.5

21

Table 13. Enable Input Truth Table1

P/N

EN11,2 EN21,2

Operation

Si8450

—

H

Outputs B1, B2, B3, B4, B5 are enabled and follow input state.

—

L

Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance

state.3

Si8451

H

X

Output A5 enabled and follow input state.

L

X

Output A5 disabled and Logic Low or in high impedance state.3

X

H

Outputs B1, B2, B3, B4 are enabled and follow input state.

X

L

Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state.3

Si8452

H

X

Outputs A4 and A5 are enabled and follow input state.

L

X

Outputs A4 and A5 are disabled and Logic Low or in high impedance state.3

X

H

Outputs B1, B2, B3 are enabled and follow input state.

X

L

Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.3

Si8455

—

—

Outputs B1, B2, B3, B4, B5 are enabled and follow input state.

Notes:

1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are

internally pulled-up to local VDD by a 3 µA current source allowing them to be connected to an external logic level (high

or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If

EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si845x is

operating in a noisy environment.

2. X = not applicable; H = Logic High; L = Logic Low.

3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled

(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See

"3. Errata and Design Migration Guidelines" on page 26 for more details.