AD660 datasheet(14/21 Pages) AD

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AD660

Rev. B | Page 13 of 20

HBE

CONTROL

LOGIC

SER

CLR

LDAC

REF IN

50Ω

REF OUT

AD660

AD688

SOUT

VOUT

AGND

SPAN/

BIPOLAR

OFFSET

DGND

–VEE

+VCC

+VLL

10V REF

16-BIT LATCH

16-BIT DAC

OUTPUT

0V TO 10V

100Ω

10kΩ

–VS

+VS

10kΩ

10.05kΩ

DB1/DB9/

DATADIR

LBE/

CLEAR SELECT

DB0/

DB8/

SIN

DB7/

DB15

16-BIT LATCH

Figure 13. Using the AD660 with the AD688 High Precision ±10 V Reference

OUTPUT SETTLING AND GLITCH

The AD660 output buffer amplifier typically settles to within

0.0008% FS (1/2 LSB) of its final value in 8 μs for a full-scale

step. Figure 14 and Figure 15 show settling for a full-scale and

an LSB step, respectively, with a 2 kΩ, 1000 pF load applied.

The guaranteed maximum settling time at 25°C for a full-scale

step is 13 μs with this load. The typical settling time for a 1 LSB

step is 2.5 μs.

The digital-to-analog glitch impulse is specified as 15 nV-s

typical. Figure 16 shows the typical glitch impulse characteristic

at the 011…111 to 100…000 code transition when loading the

second rank register from the first rank register.

+10

600

400

200

–200

–400

–600

–10

010

TIME (µs)

Figure 14. −10 V to +10 V Full-Scale Step Settling

TIME (µs)

600

400

200

–200

–400

–600

Figure 15. LSB Step Settling

+10

–10

TIME (µs)

Figure 16. Output Characteristics

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