AD660 datasheet(18/21 Pages) AD

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AD660

Rev. B | Page 17 of 20

BOARD LAYOUT

Designing with high resolution data converters requires careful

attention to board layout. Trace impedance is the first issue. A

306 μA current through a 0.5 Ω trace develops a voltage drop of

153 μV, which is 1 LSB at the 16-bit level for a 10 V full-scale

span. In addition to ground drops, inductive and capacitive

coupling need to be considered, especially when high accuracy

analog signals share the same board with digital signals. Finally,

power supplies need to be decoupled to filter out ac noise.

Analog and digital signals should not share a common path.

Each signal should have an appropriate analog or digital return

routed close to it. Using this approach, signal loops enclose a

small area, minimizing the inductive coupling of noise. Wide

PC tracks, large gauge wire, and ground planes are highly

recommended to provide low impedance signal paths. Separate

analog and digital ground planes should also be used, with a

single interconnection point to minimize ground loops. Analog

signals should be routed as far as possible from digital signals

and should cross them at right angles.

One feature that the AD660 incorporates to help the user layout

is that the analog pins (+VCC, −VEE, REF OUT, REF IN, SPAN/

BIPOLAR OFFSET, VOUT and AGND) are adjacent to help

isolate analog signals from digital signals.

SUPPLY DECOUPLING

The AD660 power supplies should be well filtered, well regulated,

and free from high frequency noise. Switching power supplies

are not recommended due to their tendency to generate spikes,

which can induce noise in the analog system.

Decoupling capacitors should be used in very close layout

proximity between all power supply pins and ground. A 10 μF

tantalum capacitor in parallel with a 0.1 μF ceramic capacitor

provides adequate decoupling. VCC and VEE should be bypassed

to analog ground, while VLL should be decoupled to digital ground.

An effort should be made to minimize the trace length between

the capacitor leads and the respective converter power supply

and common pins. The circuit layout should attempt to locate

the AD660, associated analog circuitry, and interconnections as

far as possible from logic circuitry. A solid analog ground plane

around the AD660 will isolate large switching ground currents.

For these reasons, the use of wire wrap circuit construction is

not recommended; careful printed circuit construction is

preferred.

GROUNDING

The AD660 has two ground pins, designated analog ground

(AGND) and digital ground (DGND.) The analog ground pin is

the high quality ground reference point for the device. Any

external loads on the output of the AD660 should be returned

to analog ground. If an external reference is used, this should

also be returned to the analog ground.

If a single AD660 is used with separate analog and digital ground

planes, connect the analog ground plane to AGND and the digital

ground plane to DGND keeping lead lengths as short as possible.

Then connect AGND and DGND together at the AD660. If

multiple AD660 devices are used or the AD660 shares analog

supplies with other components, connect the analog and digital

returns together once at the power supplies rather than at each

chip. This single interconnection of grounds prevents large

ground loops and consequently prevents digital currents from

flowing through the analog ground.

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