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HT48C06 Datasheet(PDF) 14 Page - Holtek Semiconductor Inc |
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HT48C06 Datasheet(HTML) 14 Page - Holtek Semiconductor Inc |
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14 / 38 page ![]() HT48R05A-1/HT48C05/HT48R06A-1/HT48C06 Rev. 1.10 14 June 9, 2004 V D D P A 0 ~ P A 7 P B 0 ~ P B 2 P C 0 ~ P C 1 M U X M U X B Z E N ( P B 0 , P B 1 O n l y ) O P 0 ~ O P 7 T M R f o r P C 1 O n l y I N T f o r P C 0 O n l y S y s t e m W a k e - u p ( P A o n l y ) R e a d D a t a R e g i s t e r P B 0 E X T ( P B 0 , P B 1 O n l y ) D Q C K S D Q C K S C o n t r o l B i t P U D a t a B u s W r i t e C o n t r o l R e g i s t e r C h i p R e s e t R e a d C o n t r o l R e g i s t e r W r i t e D a t a R e g i s t e r D a t a B i t Q Q Input/Output Ports transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it re- ceives further transient pulse. Note that, in this operat- ing mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared au- tomatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the opera- tion mode is, writinga0toETIcan disable the interrupt service. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. The bit0~2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate PFD signals for buzzer driving. Input/Output Ports There are 13 bidirectional input/output lines in the microcontroller, labeled from PA to PC, which are mapped to the data memory of [12H], [14H] and [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be re- configured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control regis- ter bit is ²1², the input will read the pad state. If the con- trol register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 17H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or 16H) instructions. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR |
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