HT48C06 datasheet(15/38 Pages) HOLTEK

15 / 38 page

HT48R05A-1/HT48C05/HT48R06A-1/HT48C06

Rev. 1.10

June 9, 2004

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. The highest 6-bit of port C and 5 bits of port B

are not physically implemented; on reading them a

²0² is

returned whereas writing then results in a no-operation.

See Application note.

There is a pull-high option available for all I/O lines.

Once the pull-high option is selected, all I/O lines have

pull-high resistors. Otherwise, the pull-high resistors are

absent. It should be noted that a non-pull-high I/O line

operating in input mode will cause a floating state.

The PB0 and PB1 are pin-shared with BZ and BZ signal,

respectively. If the BZ/BZ option is selected, the output

signal in output mode of PB0/PB1 will be the PFD signal

generated by timer/event counter overflow signal. The

input mode always remaining its original functions.

Once the BZ/BZ option is selected, the buzzer output

signals are controlled by PB0 data register only. The I/O

functions of PB0/PB1 are shown below.

PB0 I/O

O O O O O O

PB1 I/O

O O O

I O O O

PB0/PB1 Mode

B B C

PB0 Data

0 1 D0 01

PB1 Data

x D1 xx

PB0 Pad Status

0 B D0 0B

PB1 Pad Status

I D1 0B

Note:

I: input; O: output; D, D0,D1: data;

B: buzzer option, BZ or BZ; x: don't care

C: CMOS output

The PC0 and PC1 are pin-shared with INT, TMR and

pins respectively.

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

Low Voltage Reset

- LVR

The microcontroller provides low voltage reset circuit in

order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

0.9V~VLVR, such as changing a battery, the LVR will au-

tomatically reset the device internally.

The LVR includes the following specifications:

· The low voltage (0.9V~V

LVR) has to remain in their

original state to exceed 1ms. If the low voltage state

does not exceed 1ms, the LVR will ignore it and do not

perform a reset function.

· The LVR uses the

²OR² function with the external

RES signal to perform chip reset.

The relationship between VDD and VLVR is shown below.

Note:

VOPR is the voltage range for proper chip opera-

tion at 4MHz system clock.

5 . 5 V

3 . 0 V

2 . 2 V

0 . 9 V

V D D

V O P R

V L V R

5 . 5 V

V D D

5 . 5 V

V L V R

0 . 9 V

0 V

R e s e t S i g n a l

R e s e t

* 1

* 2

N o r m a l O p e r a t i o n

R e s e t

L V R D e t e c t V o l t a g e

Low Voltage Reset

Note:

*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of

1024 system clock pulses before entering the normal operation.

*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms

delay enters the reset mode.

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