TMS57014A

DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER

SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995

4

POST OFFICE BOX 655303

reset / initialization (continued)

120 Cycles of Fs

5 periods max

INIT

Internal

Reset

LRCK

Figure 1. Reset Timing Relationships

timing and control

The timing and control circuit generates and distributes necessary clocks throughout this design. XIN is the

external master clock input. The sample rate of the data paths is set as LRCK = XIN/512. With a fixed

oversampling ratio of 32x and each PWM output value requiring 16 XIN cycles, the effect of changing XIN is

shown in Table 1.

The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate

master-clock frequency. Some of the functions of the converter, such as the de-emphasis filter, operate only

at the frequencies in Table 1.

Table 1. Master Clock to Sample Rate Comparison

XIN

(MHz)

256FSO

(MHz)

LRCK

(kHz)

24.5760

12.2880

48.0

22.5792

11.2896

44.1

19.3536

9.6768

37.8

16.3840

8.1920

32.0

digital-audio data interface

The conversion cycle is synchronized to the rising edge of LRCK, and the data must meet the setup

requirements specified in the timing requirements table. The input data is 16 or 18 bits with the MSB or LSB

15

14

1

0

15

14

1

0

15

14

1

0

15

14

1

0

17

16

Right Channel

Left Channel

BCK

DATA

(16-bit)

DATA

(18-bit)

LRCK

17

16

Figure 2. Audio-Data Input Timing