MB9B500B datasheet(2/115 Pages) CYPRESS

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Document Number: 002-05607 Rev. *E

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MB9B500B Series

[UART]

 Full-duplex double buffer

 Selection with or without parity supported

 Built-in dedicated baud rate generator

 External clock available as a serial clock

 Hardware Flow control: Automatically control the

transmission by CTS/RTS (only ch.4)

 Various error detect functions available (parity errors,

framing errors, and overrun errors)

[CSIO]

 Full-duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detect function available

[LIN]

 LIN protocol Rev.2.1 supported

 Full-duplex double buffer

 Master/Slave mode supported

 LIN break field generate (can be changed 13-16bit length)

 LIN break delimiter generate (can be changed 1-4bit length)

 Various error detect functions available (parity errors,

framing errors, and overrun errors)

[I2C]

 Standard-mode (Max.100 kbps) / Fast-mode (Max.400 kbps)

supported

External Bus Interface

 Supports SRAM, NOR& NAND Flash device

 Up to 8 chip selects

 8-/16-bit Data width

 Up to 25-bit Address bit

 Maximum area size: Up to 256 Mbytes

DMA Controller (8 channels)

DMA Controller has an independent bus for CPU, so CPU and

DMA Controller can process simultaneously.

 8 independently configured and operated channels

 Transfer can be started by software or request from the

built-in peripherals

 Transfer address area: 32 bit(4 Gbyte)

 Transfer mode: Block transfer/Burst transfer/Demand

transfer

 Transfer data type: byte/half-word/word

 Transfer block count: 1 to 16

 Number of transfers: 1 to 65536

A/D Converter (Max. 16 channels)

[12-bit A/D Converter]

 Successive Approximation Register type

 Built-in 3unit

 Conversion time: 1.0 μs@5 V

 Priority conversion available (priority at 2levels)

 Scanning conversion mode

 Built-in FIFO for conversion data storage (for SCAN

conversion: 16steps, for Priority conversion: 4steps)

Base Timer (Max. 8 channels)

Operation mode is selectable from the followings for each

channel.

 16-bit PWM timer

 16-bit PPG timer

 16-/32-bit reload timer

 16-/32-bit PWC timer

Multi-function Timer (Max. 2 units)

The Multi-function timer is composed of the following blocks.

 16-bit free-run timer × 3 ch/unit

 Input capture × 4 ch/unit

 Output compare × 6 ch/unit

 A/D activation compare × 3 ch/unit

 Waveform generator × 3 ch/unit

 16-bit PPG timer × 3 ch/unit

MB9B500B Datasheet(PDF) 2 Page - Cypress Semiconductor

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