DS3153N datasheet(16/60 Pages) DALLAS

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

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Status Register Description

The status registers have two types of status bits. Real-time status bits—located in the SRn registers—indicate the

state of a signal at the time it was read. Latched status bits—located in the SRLn registers—are set when a signal

changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1

value. After clearing, latched status bits remain cleared until the signal changes state again. Interrupt-enable bits—

located in the SRIEn registers—control whether or not the

INT pin is driven low when latched register bits are set.

Figure 5-1. Status Register Logic

GCRn

Global Configuration Register

00h, 10h, 20h, 30h

Bit

Name

E3M

STS

LLB

RLB

TDSA

TDSB

—

RST

Default

—

Bit 7: E3 Mode Enable (E3M)

0 = DS3 operation

1 = E3 or STS-1 operation

Bit 6: STS-1 Mode Enable (STS)

When E3M = 1,

0 = E3 operation

1 = STS-1 operation

When E3M = 0, STS selects the DS3 AIS pattern (Table 4-F).

Bits 5, 4: Local Loopback, Remote Loopback Select (LLB, RLB)

00 = no loopback

01 = remote loopback

10 = analog local loopback

11 = digital local loopback

Bits 3, 2: Transmitter Data Select (TDSA, TDSB). See Table 4-F for details.

Bit 0: Reset (RST). When this bit is high, the digital logic of the LIU is held in reset and all registers for that LIU

(except the RST bit) are forced to their default values. RST is cleared to 0 at power-up and when the

RST pin is

activated.

0 = normal operation

1 = reset LIU

EVENT

LATCHED STATUS REGISTER

SET ON EVENT DETECT CLEAR

ON WRITE LOGIC 1

INT ENABLE

SRL

INT

OTHER INT

SOURCE

REAL-TIME STATUS

LATCHED STATUS

DS3153N Datasheet(PDF) 16 Page - Dallas Semiconductor

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