DS3153N datasheet(24/60 Pages) DALLAS

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

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§ ITU bit set to 1

–

A BPV with the same polarity as the last BPV.

When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last

BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.

To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be inverted.

Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on

these pins on the rising edge of RCLK, pull the RCINV pin high (hardware mode) or set the RCINV configuration bit

(CPU bus mode).

The RCLK, RPOS/RDAT, and RNEG/RLCV pins can be tri-stated to support protection switching and redundant-

LIU applications. This tri-stating capability supports system configurations where two or more LIUs are wire-ORed

together and a system processor selects one to be active. To tri-state RCLK, RPOS/RDAT, and RNEG/RLCV,

assert the

RTS pin or the RTS configuration bit.

Receive Line-Code Violation Counter. The line-code violation counter is always enabled regardless of the

settings of the RBIN pin or the RBIN configuration bit. The receiver has an internal 16-bit saturating counter and a

16-bit latch, which the CPU can read as registers RCVH and RCVL. The value of the internal counter is latched into

the RCVH/RCVL register and cleared when the receive code-violation counter update bit, RCVUD, is changed from

a zero to a one. The RCVUD bit must be cleared back to a zero before a new update can occur. If there is an LCV

increment pulse and an update pulse in the same clock period, the counter is preset to a one rather than cleared

so that the LCV is not missed. The counter is incremented when the RLCV pin flags a code violation as described

in the Framer Interface Format and the B3ZS/HDB3 Decoder section. The counter saturates at 65,535 (0FFFFh)

and does not roll over.

Receiver Power-Down. To minimize power consumption when the receiver is not being used, assert the RPD

configuration bit (CPU bus mode). When the receiver is powered down, the RCLK, RPOS/RDAT, and RNEG/RLCV

pins are tri-stated. In addition, the RXP and RXN pins become high impedance.

Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all applicable

telecommunication standards in Table 1-A. See Figure 6-1.

Figure 6-1. Receiver Jitter Tolerance

100

10k

100k

60k

22.3k

2.3k

669

0.1

1.0

300k

800k

300

0.1

0.15

0.3

1.5

E3 G.823

DS3 GR-499 Cat II

DS3 GR-499 Cat I

DS315x JITTER TOLERANCE

STS-1 GR253

FREQUENCY (Hz)

DS3153N Datasheet(PDF) 24 Page - Dallas Semiconductor

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