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MAX1121 Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX1121 Datasheet(HTML) 3 Page - Maxim Integrated Products |
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3 / 17 page ![]() 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guar- anteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Duty Cycle Set by clock management circuit 40 to 60 % Aperture Delay tAD 350 ps Aperture Jitter tAJ 0.2 psRMS CLOCK INPUTS (CLKP, CLKN) Differential Clock Input Amplitude (Note 2) 200 500 mVP-P Clock Input Common-Mode Voltage Range 1.25 ±0.25 V Clock Differential Input Resistance RCLK 11 ±25% k Ω Clock Differential Input Capacitance CCLK 5pF DYNAMIC CHARACTERISTICS (at -0.5dBFS) fIN = 10MHz, TA ≥ +25°C 47.2 48.9 fIN = 100MHz, TA ≥ +25°C 46.2 48.8 fIN = 180MHz 48.8 Signal-to-Noise Ratio SNR fIN = 500MHz 48.7 dB fIN = 10MHz, TA ≥ +25°C 47.1 48.8 fIN = 100MHz, TA ≥ +25°C 46.1 48.7 fIN = 180MHz 48.7 Signal-to-Noise and Distortion SINAD fIN = 500MHz 48.6 dB fIN = 10MHz, TA ≥ +25°C60 69 fIN = 100MHz, TA ≥ +25°C59 68 fIN = 180MHz 69.1 Spurious-Free Dynamic Range SFDR fIN = 500MHz 63.8 dBc fIN = 10MHz -74.6 fIN = 100MHz -68.4 fIN = 180MHz -69.1 Worst Harmonics (HD2 or HD3) fIN = 500MHz -63.8 dBc IMD100 fIN1 = 99MHz at -7dBFS, fIN2 = 101MHz at -7dBFS -70 Two-Tone Intermodulation Distortion IMD500 fIN1 = 498.5MHz at -7dBFS, fIN2 = 502.5MHz at -7dBFS -56 dBc LVDS DIGITAL OUTPUTS (D0P/N–D7P/N, DCLKP/N) Differential Output Voltage |VOD| 250 400 mV |
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