1.8V, 8-Bit, 250Msps Analog-to-Digital Converter

with LVDS Outputs for Wideband Applications

4

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ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output Offset Voltage

1.125

1.310

V

LVCMOS DIGITAL INPUTS (CLKDIV,

T/B)

Digital Input Voltage Low

0.2 x

V

Digital Input Voltage High

0.8 x

V

TIMING CHARACTERISTICS

CLK to Data Propagation Delay

Figure 4

1.5

ns

CLK to DCLK Propagation Delay

Figure 4

2.85

ns

Data Valid to DCLK Rising Edge

Figure 4 (Note 2)

0.92

1.35

1.86

ns

LVDS Output Rise-Time

460

ps

LVDS Output Fall-Time

460

ps

Output Data Pipeline Delay

8

Clock

cycles

POWER REQUIREMENTS

Analog Supply Voltage Range

1.70

1.80

1.90

V

Digital Supply Voltage Range

1.70

1.80

1.90

V

Analog Supply Current

220

290

mA

Digital Supply Current

45

75

mA

Analog Power Dissipation

477

657

mW

Offset

1.6

mV/V

Power-Supply Rejection Ratio

(Note 3)

PSRR

Gain

1.9

%FS/V

Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-

scale range is defined as 1023 x slope of the line.

Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.