SMP9410F datasheet(2/13 Pages) ETC

2 / 13 page

SMP9410

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

2056 2.0 10/04/02

PIN CONFIGURATION

1.25VREF

VOUT0

VOUT1

VOUT2

VOUT3

SDA

SCL

2056 PCon-F

QFN

TQFP

INTRODUCTION

The device has four 10-Bit digital to analog converters that

are comprised of a resistor network that converts a digital

input into an equivalent analog output voltage in proportion

to the applied reference voltages. The voltage differential

between each VREFL and VREFH input pair sets the range

and full-scale output voltage for their respective DAC.

Each DAC has a 10-Bit nonvolatile register that can hold a

‘set-and-forget’ value that can be recalled whenever the

device is powered-on.

Each DAC has a 10-Bit volatile register that holds the

current digital value. The register can be set to any value

by the serial interface; commanded to load the zero scale

value, full scale value or mid-scale value; or can recall a

preset value stored in a nonvolatile register.

The device also has a nonvolatile configuration register that

is accessible over the 2-wire bus. The configuration register

is used to select the device type identifier and the DAC

power-on state.

The device uses the industry standard I2C 2-wire serial

protocol. The bus is designed for two-way, two-line serial

communication between different integrated circuits. The

two lines are the SCL (serial clock) and SDA (serial data).

Both lines should be pulled up to the positive supply through

a resistor. The protocol defines devices as being either

Masters or Slaves. The SMP9410 will always be a Slave

because it does not initiate any communications or provide

a clock output.

DEVICE OPERATION

TOP VIEW

SDA

SCL

VREFH3

1.25VREF

VOUT0

VOUT1

VOUT2

VOUT3

2056 PCon-L

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