SMP9410F datasheet(8/13 Pages) ETC

8 / 13 page

SMP9410

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

2056 2.0 10/04/02

ACCESSING THE DACS

Data transfers are initiated when a Master issues a Start

condition, which is a high to low transition on SDA while

SCL is high (see Figure 3). The Start is immediately

followed by an eight bit transmission: bits 7 through 1

comprise the device type identifier and device bus address;

bit 0 is the Read/Write bit indicating the action to follow. If

the intended device receives the byte and recognizes its

address it will return an Acknowledge during the 9th clock

cycle. Some data transfers will be concluded with a Stop

condition, which is a low to high transition on SDA while

SCL is high. Note: a Stop condition must be performed for

all nonvolatile Write operations. Timing for all I2C opera-

tions are summarized in Figure 4 and Table 1.

The default device type identifier for addressing DACs is

0101BIN. In order to accommodate more than eight devices

on a single bus the device type identifier can be modified by

the end user by writing to the configuration registers. (See

Table 2). A0, A1 and A2 are the address inputs. When

addressing the nonvolatile or configuration registers,

theaddress inputs distinguish which one of eight possible

devices sharing the common bus is being addressed.

Setting them high or low will determine the device’s bus

address that is contained within the serial bus data stream.

Figure 3. START and STOP Timing

Figure 4. I2C Data/Clock Timing

2056 Fig01

SCL

SDA In

START

Condition

STOP

Condition

tLOW

tHIGH

tHD:STA

tSU:STA

tBUF

tDH

tHD:DAT

tSU:DAT

tSU:STO

SCL

SDA In

SDA Out

tAA

2056 Fig02

Command Structure

The command structure is illustrated in Table 2. Of special

note is the ability to write individually to any of the four

DACs, or to all of them. The first five commands are three

bytes in length and can either be volatile or nonvolatile DAC

writes.

APPLICATIONS INFORMATION (CONTINUED)

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