AD9876BST datasheet(15/24 Pages) AD

15 / 24 page

REV. A

AD9876

–15–

TRANSMIT PATH

The AD9876 transmit path consists of a digital interface port, a

programmable interpolation filter, and a transmit DAC. All

clock signals required by these blocks are generated from the

fOSCIN signal by the PLL-A clock generator. The block diagram

below shows the interconnection between the major functional

components of the transmit path.

TxDAC+

Kx INTERPOLATION

LPF/BPF

CLOCK GEN

PLL-A

Tx+

Tx–

OSCIN

XTAL

Tx QUIET

GAIN

Tx [5:0]

Tx SYNC

CLK-A

DAC = L

OSCIN

DEMUX

AD9876

Figure 1. Transmit Path Block Diagram

DIGITAL INTERFACE PORT

The Transmit Digital Interface Port has several modes of opera-

tion. In its default configuration, the Tx Port accepts six bit

nibbles through the Tx [5:0] and Tx SYNC pins and demul-

tiplexes the data into 12-bit words before passing it to the

interpolation filter. The input data is sampled on the rising edge

of fCLK-A.

Additional programming options for the Tx Port allow: sampling

the input data on the falling edge of fCLK-A, inversion or disabling

of fCLK-A, and reversing the order of the nibbles. Also, the Tx Port

interface can be controlled by the GAIN pin to provide direct

access to the Rx Path Gain Adjust Register. All of these modes

are fully described in the Register Programming Definitions sec-

tion of this data sheet.

The data format is twos complement, as shown below:

011 . . 11: Maximum

000 . . 01: Midscale + 1 LSB

000 . . 00: Midscale

111 . . 11: Midscale – 1 LSB

111 . . 10: Midscale – 2 LSB

100 . . 00: Minimum

The data can be translated to a straight binary data format by

simply inverting the most significant bit.

The timing of the interface is fully described in the Transmit

Port Timing section of this data sheet.

PLL-A CLOCK DISTRIBUTION

Figure 1 shows the clock signals used in the transmit path. The

DAC sampling clock, fDAC, is generated by PLL-A. fDAC has a

frequency equal to L

× fOSCIN, where fOSCIN is the internal signal

generated either by the crystal oscillator when a crystal is con-

nected between the OSCIN and XTAL pins, or by the clock that

is fed into the OSCIN pin, and L is the multiplier programmed

through the serial port. L can have the values of 1, 2, 4, or 8.

The transmit path expects a new half-word of data at the rate

of fCLK-A. When the Tx multiplexer is enabled, the frequency

of Tx Port is:

CLK A

DAC

OSCIN

−

=×

=× ×

where K is the interpolation factor that can be programmed to be

1, 2, or 4. When the Tx multiplexer is disabled, the frequency of

the Tx Port is:

CLK A

DAC

OSCIN

−

== ×

Note, this will result in a 6-bit data path.

INTERPOLATION FILTER

The interpolation filter can be programmed to run at 2

× and 4×

upsampling ratios in each of three different modes. The transfer

functions of these six configurations are shown in TPCs 1–6.

The X-axis of each of these figures corresponds to the frequency

normalized to fDAC. These transfer functions show both the

discrete time transfer function of the interpolation filters alone

and with the SIN(x)/x transfer function of the DAC. The

interpolation filter can also be programmed into a pass-

through mode if no interpolation filtering is desired.

The contents of the interpolation filter are not cleared by

hardware or software resets. It is recommended to “flush” the

transmit path with zeros before transmitting data.

The table below contains the following parameters as a function

of the mode that it is programmed.

Latency – The number of clock cycles from the time a digital

impulse is written to the DAC until the peak value is output at

the T+ and T– pins.

Flush – The number of clock cycles from the time a digital

impulse is written to the DAC until the output at the Tx+ and

Tx– pins settles to zero.

fLOWER (0.1 dB, 3 dB) – This indicates the lower 0.1 dB or 3 dB

cutoff frequency of the interpolation filter as a fraction of fDAC,

the DAC sampling frequency.

fUPPER (0.1 dB, 3 dB) – This indicates the upper 0.1 dB or 3 dB

cutoff frequency of the interpolation filter as a fraction of fDAC,

the DAC sampling frequency.

Table I. Interpolation Filter Parameters vs. Mode

Mode

× LPF 2 × LPF 4 × BPF 2 × BPF 4 × BPF 4 × BPF

Adj.

Lower

Upper

Latency, fDAC

Clock Cycles

Flush, fDAC

128

148

142

Clock Cycles

fLOWER, 0.1 dB

0.398

0.276

0.148/

0.274/

0.774

0.648

fUPPER, 0.1 dB

0.102

0.204

0.602

0.724

0.226/

0.352/

0.852

0.762

fLOWER, 3 dB

0.381

0.262

0.131/

0.257/

0.757

0.631

fUPPER, 3 dB

0.119

0.238

0.619

0.738

0.243/

0.369/

0.869

0.743

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