LTC1923 datasheet(9/28 Pages) LINER

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LTC1923

1923f

PI FU CTIO S

NDRVA, NDRVB (Pins 21, 24/Pins 19, 23): These push-

pull outputs are configured to drive the opposite low side

switches in a full-bridge arrangement.

PGND (Pin 22/Pin 20): This is the high current ground for

the IC. The external current sense resistor should be

referenced to this point.

VDD (Pin 23/Pins 21, 22): Positive Supply Rail for the IC.

Bypass this pin to PGND and AGND with > 10

µF low ESL,

ESR ceramic capacitors. The turn on voltage level for VDD

is 2.6V with 130mV of hysteresis.

VREF (Pin 26/Pin 27): This is the output of the Reference.

This pin should be bypassed to GND with a 1

µF ceramic

capacitor. The reference is able to supply a minimum of

10mA of current and is internally short-circuit current

limited.

CT (Pin 27/Pin 28): The triangular wave oscillator timing

capacitor pin is used in conjunction with RT to set the

oscillator frequency. The equation for calculating fre-

quency is:

OSC

075

•

RT (Pin 28/Pin 29): A single resistor from RT to AGND sets

the charging and discharging currents for the triangle

oscillator. This pin also sets the dead time between turning

one set of outputs off and turning the other set on to ensure

the outputs do not cross conduct. The voltage on this pin

is regulated to 0.5V. For best performance, the current

sourced from the RT pin should be limited to a maximum

150

µA. Selecting RT to be 10k is recommended and

provides 90ns of dead time.

VTEC (Pin 14/Pin 12): Output of the differential TEC voltage

amplifier equal to the magnitude of the voltage across

the TEC.

TEC– (Pin 15/Pin 13): Inverting Input to the Differential TEC

Voltage Amplifier. This amplifier has a fixed gain of 1 with its

output being the voltage across the TEC with respect to

AGND. This input, along with TEC+, signifies whether the

TEC is heating or cooling the laser as indicated by the

H/C pin.

TEC+ (Pin 16/Pin 14): Noninverting Input to the Differen-

tial TEC Voltage Amplifier.

ITEC (Pin 17/Pin 15): Output of the Differential Current

Sense Amplifier. The voltage on this pin is equal to 10 •

(ITEC + IRIPPLE) • RS, where ITEC is the thermoelectric

cooler current, IRIPPLE is the inductor ripple current and RS

is the sense resistor used to sense this current. This

voltage represents only the magnitude of the current and

provides no direction information. Current limit occurs

when the voltage on this pin exceeds the lesser of 1.5

times the voltage on SS, 1.5 times the voltage on ILIM or

1.5V. When this condition is present, the pair of outputs,

which are presently conducting, are immediately turned

off. The current limit condition is cleared when the CT pin

reaches the next corresponding peak or valley (see Cur-

rent Limit section).

CS – (Pin 18/Pin 16): Inverting Input to the Differential

Current Sense Amplifier.

CS+ (Pin 19/Pin 17): Noninverting Input of the Differential

Current Sense Amplifier. The amplifier has a fixed gain

of 10.

PDRVA, PDRVB (Pins 20, 25/Pins 18, 24): These push-

pull outputs are configured to drive the opposite high side

PMOS switches in a full-bridge arrangement.

(GN Package/UH Package)

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