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LTC1923

1923f

Transistor M1 is off and the current limit threshold is given

by:

LIMIT

ILIM

REF

ILIM

()

015

.•

•

When TEC– is greater than TEC+, the open-drain output,

H/C, pulls high through RPULLUP, causing M1 to turn on.

The current limit value is given by:

LIMIT

ILIM

REF

ILIM

()

015

.•

•

reducing the current limit threshold for heating. If the

heating current limit needs to be greater than the cooling

limit, an extra inversion can be added.

Open/Shorted Thermistor Detection

The temperature sense element (NTC thermistor, plati-

num RTD or other appropriate component) must be prop-

erly connected in order for the system to regulate

temperature. If the sense element is incorrectly con-

nected, the system will be unable to control the tempera-

ture and the potential exists for the system to thermally run

away.

A TEC by nature produces a temperature differential be-

tween opposite sides of the device depending upon how

much current is flowing through it. There is a maximum

limit to the amount of temperature differential that can be

produced, which depends upon a number of physical

OPERATIO

parameters including the size of the TEC and how well

heatsinked the device is. The TEC itself dissipates power

to produce the temperature differential, generating heat,

which must also be removed. At a certain level of power

dissipation in the TEC, both sides will begin to heat. This

is because the TEC will not be able to pump the self-

generated heat to the outside world, which can lead to

thermal runaway. If the device thermally runs away, dam-

age to the TEC and possibly the components whose

temperature is being regulated will occur.

The LTC1923 contains two dedicated comparators that

directly monitor the voltage on the thermistor. If this

voltage is outside the valid window, a latch is set and the

FAULT pin is asserted low. The output drivers are not shut

off and the control circuitry is not disabled, meaning the

part will continue to try to regulate temperature. It is up to

the user to use the FAULT signal to disable the appropriate

circuitry. There are a couple of ways to do this. The first

way is to have the FAULT signal a system microprocessor

to shut the system down through the SDSYNC pin. Fig-

ure 5 shows another means of protecting the system.

External NMOS M1 and PMOS M2 have been added along

with two pull-up resistors (RP1 and RP2). M1 and RP2

invert the FAULT signal while M2 acts as a switch in series

with bridge. When no fault is present, the gate of M1 is

–

H/C

2N7002

LTC1923

ILIM

TEC+

TEC –

1923 F04

RLIM3

RILIM1

RILIM2

VREF

VDD

RPULLUP

Figure 4. Independently Heating/Cooling Current Limit

1923 F05

NDRVB

NDRVA

CS+

CS–

PDRVA

PDRVB

FAULT

RP2

TEC

VDD

RP1

Figure 5. Redundant Fault Protection

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