Pad Coordinates

Unit:

mm

Pad No.

X

Y

Pad No.

X

Y

1

-1110.000

555.300

27

977.250

-720.000

2

-1110.000

450.300

28

977.250

-612.000

3

-1110.000

345.300

29

977.250

-504.000

4

-1110.000

240.300

30

977.250

-396.000

5

-1110.000

135.300

31

977.250

-288.000

6

-1165.900

9.800

32

977.250

-180.000

7

-1110.000

-125.500

33

977.250

-55.150

8

-1110.000

-230.500

34

977.250

49.850

9

-1110.000

-335.500

35

977.250

173.350

10

-1110.000

-440.500

36

977.250

281.350

11

-1110.000

-545.500

37

977.250

389.350

12

-1110.000

-650.500

38

977.250

497.350

13

-1110.000

-755.500

39

977.250

605.350

14

-897.200

-560.300

40

977.250

713.350

15

-782.500

-560.300

41

405.500

545.400

16

-674.500

-560.300

42

297.500

545.400

17

-566.500

-560.300

43

189.500

545.400

18

-458.500

-560.300

44

81.500

545.400

19

-350.500

-560.300

45

-34.700

545.400

20

-242.500

-560.300

46

-173.950

684.850

21

-134.500

-560.300

47

-285.150

684.850

22

-26.500

-560.300

48

-390.150

684.850

23

81.500

-560.300

49

-501.350

684.850

24

189.500

-560.300

50

-606.350

684.850

25

297.500

-560.300

51

-765.200

726.350

26

405.500

-560.300

Pin Description

Pin No.

Pin Name

I/O

Description

1~4

SW1~SW4

I

4-bit general purpose input port

5DO

O

Output serial data at the falling edge of the shift clock, starting from low order

bit. This is an NMOS open-drain output pin.

6DI

I

Input serial data at the rising edge of the shift clock, starting from the low order

bit.

7NC

¾ No connection

8

CLK

I

Reads serial data at the rising edge, and outputs data at the falling edge.

9CS

I

Initializes serial interface at the rising or falling edge of the HT16511. Then it

waits to receive a command. Data input after CS has fallen is processed as a

command. While command data is processed, current processing is stopped,

and the serial interface is initialized. While CS is high, CLK is ignored.

10~13

K0~K3

I

Keying data input to these pins is latched at the end of the display cycle.

14, 33, 45 VDD

¾ Posistive power supply

15~26

S1/K1~S12/K12

O

Segment or key source output pins (dual function). This is PMOS open-drain

and pull-low resistor output.

27~32,

35~36

S13/G16~S20/G9

O

Segment or Grid driver output pins. These pins are selectable for segment or

grid driving. This is PMOS open-drain and pull-low resistor output.

34

VEE

¾ VFD power supply

37~44

G8~G1

O

Grid driver output pins (Grid only). This is PMOS open-drain and pull-low re-

sistor output.

46~50

LED4~LED0

O

LED driver output ports. This is a CMOS output pin.

51

VSS

¾ Negative power supply, ground

52

OSC

I

Connected to an external resistor or an RC oscillator circuit.

HT16511

Rev. 1.10

3

September 18, 2003