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MACH11SP Datasheet(PDF) 13 Page - List of Unclassifed Manufacturers

Part # MACH11SP
Description  High-Performance EE CMOS In-System Programmable Logic
PDF  33 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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MACH11SP Datasheet(HTML) 13 Page - List of Unclassifed Manufacturers

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V
ANTIS
MACH211SP-7/10/12/15 (Com’l)
13
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
f = 1 MHz
6
pF
COUT
Output Capacitance
VOUT = 2.0 V
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
-7
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
7.5
10
12
15
ns
tS
Setup Time from Input, I/O, or Feedback
to Clock (Note 3)
D-type
5.5
6.5
7
10
ns
T-type
6.5
7.5
8
11
ns
tH
Register Data Hold Time
0
0
0
0
ns
tCO
Clock to Output (Note 3)
4.5
6
8
10
ns
tWL
Clock Width
LOW
3
5
6
6
ns
tWH
HIGH
3
5
6
6
ns
fMAX
Maximum
Frequency
(Note 1)
External
Feedback
1/(tS + tCO)
D-type
100
80
66.7
50
MHz
T-type
91
74
62.5
47.6
MHz
Internal Feedback (fCNT)
D-type
133
100
83.3
66.6
MHz
T-type
125
91
76.9
62.5
MHz
No
Feedback
1/(tWL + tWH)
166.7
100
83.3
83.3
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
5.5
6.5
7
10
ns
tHL
Latch Data Hold Time
0
0
0
0
ns
tGO
Gate to Output
7
7
10
11
ns
tGWL
Gate Width LOW
3
5
6
6
ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
9.5
12
14
17
ns
tSIR
Input Register Setup Time
2
2
2
2
ns
tHIR
Input Register Hold Time
2
2
2
2.5
ns
tICO
Input Register Clock to Combinatorial Output
11
13
15
18
ns
tICS
Input Register Clock to Output Register
Setup
D-type
9
10
12
15
ns
T-type
10
11
13
16
ns
tWICL
Input Register Clock Width
LOW
3
5
6
6
ns
tWICH
HIGH
3
5
6
6
ns
fMAXIR
Maximum Input Register Frequency
166.7
100
83.3
83.3
MHz
tSIL
Input Latch Setup Time
2
2
2
2
ns
tHIL
Input Latch Hold Time
2
2
2
2.5
ns
tIGO
Input Latch Gate to Combinatorial Output
12
14
17
20
ns



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