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MM74C95 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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MM74C95 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 4 page ![]() AC Electrical Characteristics TA e 25 C CL e 50 pF unless otherwise noted Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay Time to a Logical VCC e 5V 200 400 ns ‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q VCC e 10V 80 160 ns tS0 tS1 Time Prior to Clock Pulse that Data VCC e 5V 60 30 ns must be Preset VCC e 10V 25 10 ns tH0 tH1 Time After Clock Pulse that Data VCC e 5V 25 10 ns must be Held VCC e 10V 10 50 ns tPW Minimum Clock Pulse Width (tWL e tWH)VCC e 5V 100 ns VCC e 10V 50 ns tSM Time Prior to Clock Pulse that Mode VCC e 5V 200 100 ns Control must be Preset VCC e 10V 100 50 ns fMAX Maximum Input Clock Frequency VCC e 5V 3 5 MHz VCC e 10V 65 10 MHz CIN Input Capacitance Any Input (Note 2) 5 pF CPD Power Dissipation Capacitance (Note 3) 100 pF AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C74C Family Characteristics Application Note AN-90 Function Table Inputs Outputs Mode Clocks Serial Parallel QA QB QC QD Control 2 (L) 1 (R) A B C D HH X X X X X X QA0 QB0 QC0 QD0 H v XX a b c c a b c d H v XX QB QC QD dQBn QCn QDn d LL H X X X X X QA0 QB0 QC0 QD0 LX v HX X X X H QAn QBn QCn LX v LX X X X L QAn QBn QCn u LL X X X X X QA0 QB0 QC0 QD0 v LL X X X X X QA0 QB0 QC0 QD0 v LH X X X X X QA0 QB0 QC0 QD0 u HL X X X X X QA0 QB0 QC0 QD0 u HH X X X X X QA0 QB0 QC0 QD0 u L H X X X X X Undefined v H L X X X X X Operating Conditions Shifting left requires external connection of QB to A QC to B and QD to C Serial data is entered at input D H e high level (steady state) L e low level (steady state) X e irrelevant (any input including transitions) v e transition from high to low level u e transition from low to high level a b c d e the level of steady-state input at inputs A B C or D respectively QA0 QB0 QC0 QD0 e the level of QA QB QC or QD respectively before the indicated steady-state input conditions were established QAn QBn QCn QDn e the level of QA QB QC or QD respectively before the most recent transition of the clock 3 |
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