OV6120 datasheet(14/31 Pages) ETC

14 / 31 page

OV6620/OV6120

Version 1.11

14 May 1999

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OMNIVISION TECHNOLOGIES, Inc.

Advanced Information

Preliminary

1.2.7

Slave Mode Operation

The OV6620/OV6120 sensors can be programmable to

operate in slave mode configuration (COMI[6] = 1, de-

fault is master mode). HSYNC and VSYNC output sig-

nals are provided.

When used as a slave device, the external master must

provide the OV6620/OV6120 imager with the following:

1. System clock CLK to XCLK1 pin;

2. Horizontal sync, Hsync, to CHSYNC pin, positive

assertion;

3. Vertical frame sync, Vsync, to VSYNC pin,

positive assertion

When in slave mode, the OV6620/OV6120 tri-states

CHSYNC (pin 42) and VSYNC (pin 16) output pins,

which may then be used as input pins. To synchronize

multiple devices, the OV6620/OV6120 image sensors

use external system clock, CLK, to synchronize external

horizontal sync, HSYNC, which is then used to synchro-

nize external vertical frame sync, Vsync. See Figure 5,

Slave Mode External Sync Timing for timing consider-

ations.

1.2.8

Frame Exposure Mode

The OV6620/OV6120 sensors support frame exposure

mode when programmed for Progressive Scan. FREX

(pin 4) is asserted by an external master device to set

exposure time. When FREX = 1, the OV6620/OV6120

pixel array will be quickly precharged. Based on the ex-

ternal master’s assertion of FREX, the OV6620/OV6120

devices capture the image. When the master de-asserts

FREX (FREX = 0), the video output data stream is deliv-

ered to the OV6620/OV6120 output port in a line-by-line

manner.

It should be noted that FREX must active long enough

to ensure the complete image array has been pre-

charged.

When data is being output from the OV6620/OV6120

image sensor, care must be taken so as not to expose

the image array to light. This may affect the integrity of

the image data captured. A mechanical shutter synchro-

nized with the frame exposure rate can be used to min-

imize this situation. Frame exposure mode timing is

shown in Section Figure 6. Frame Exposure Timing be-

low.

1.2.9

Reset

The OV6620/OV6120 image sensor includes a RESET

pin (pin 2) which forces a complete hardware reset when

pulled high (Vcc). When a hardware reset occurs, the

OV6620/OV6120 sensor clears all registers or sets

them to their default values. Reset may also be initiated

through the I2C interface.

1.2.10 Power Down Mode

Two methods are available for placing the OV6620/

OV6120 devices into power-down mode: hardware pow-

er down and I2C/software power down.

To initiate hardware power down the PWDN pin (pin 9)

must be tied to high (+5VDC). When this occurs, the

OV6620/OV6120 internal device clock is halted and all

internal registers (except I2C registers) are reset. In this

mode, current draw is less than 10uA.

Executing a software power down through the I2C inter-

face suspends internal circuit activity, but does halt the

device clock. In this mode, current requirements drop to

less than 1mA.

1.2.11 Configuring the OV6620/OV6120 Image

Sensors

Two methods are provided for configuring the OV6620/

OV6120 IC for specific application requirements.

At power up, the OV6620/OV6120 sensor reads the sta-

tus of certain pins to determine what, if any, power up

default settings are requested. Once the reading of the

external pins is completed, the device configures its in-

ternal registers according to the specified pins. Not all

device functions are available for configuration through

external pin.

A more flexible and comprehensive method for configur-

ing the OV6620/OV6120 IC is to use its on-chip I2C reg-

ister programming capability. The I2C interface provides

access to all of the device’s programmable internal reg-

isters. See Section 3.1 I2C Bus Protocol Format for fur-

ther details about using the I2C interface on the

OV6620/OV6120 camera device.

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