SC2449 datasheet(17/20 Pages) SEMTECH

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 2002 Semtech Corp.

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POWER MANAGEMENT

SC2449

Control Loop Design (Cont.)

Step 1. Output filter corner frequency

o = 1.453 KHz

Step 2. ESR zero frequency:

esr = 2.653 KHz

Step 3. Check the following condition:

Which is satisfied in this case.

Step 4. Choose crossover frequency and calculate

compensator R:

x_over = 30 KHz

R = 5.89 KΩ

Step 5. Calculate the compensator C:

C = 92.98 n.

Step 6. Generate Bode plot and check the phase

margin. In this case, the phase margin is about 85°C

that ensures the loop stability. .ig. 2 shows the Bode

plot of the loop.

G pwm V in

G error

F o

F esr

F x_over

F o

V o

V bg

when

F esr F o

F x_over

(5) The compensation capacitor is determined by choos-

ing the compensator zero to be about one fifth of the

output filter corner frequency:

F zero

F o

. R

. F

zero

(6) The final step is to generate the Bode plot, either by

using the simulation model in .ig. 1 or using the equa-

tions provided here with Mathcad. The phase margin

can then be checked using the Bode plot. Usually, this

design procedure ensures a healthy phase margin.

An example is given below to demonstrate the proce-

dure introduced above. The parameters of the power

supply are given as:

F ers

F sw

:= 24 V

:= 2.5 V

:= 20 A

:= 150 KHz

L := 4

µH

:= 3000

µF

:= 0.02

Ω

:= 1.5 K

Ω

:= 1.0 K

Ω

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