SC2449 datasheet(18/20 Pages) SEMTECH

18 / 20 page

 2002 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC2449

Good layout is necessary for successful implementa-

tion of the SC2449 bi-phase/dual controller. Important

layout guidelines are listed below.

1). The high power parts should be laid out first. The para-

sitic inductance of the pulsating power current loop (start

from positive end of the input capacitor, to top MOS.ET,

then to bottom MOS.ET back to power ground) must be

minimized. The high frequency input capacitors and top

MOS.ETs should be close to each other. The freewheel-

ing Schottky diode, the bottom MOS.ET snubber, and

the bottom MOS.ET should be placed close to each other.

The MOS.ET gate drive and current sense loop areas

should be minimized. The gate drive trace should be

short and wide.

2). The layout of the two phases should be made as sym-

metrical as possible. The SC2449 controller should be

placed in the center of the two phases. Please see evalu-

ation board layout as an example.

3). Separate ground planes for analog and power should

be provided. Power current should avoid running over

the analog ground plane. The AGND is star connected to

the PGND at the converter output to provide best pos-

sible ground sense. Refer to the application schematics,

certain components should be connected directly to the

AGND.

4). If a multi-layer PCB is used, power layer and ground

layer are recommended to be adjacent to each other.

Typically the power layer is on the top, followed by the

ground layer. This results in the least parasitic inductance

in the MOS.ET-capacitor power loop, and reduces the

ringing on the phase node. The rest of the layers could

be used to run DC supply traces and signal traces.

An example of a two-layer PCB layout is given below to

illustrate these layout principles.

Control Loop Design (Cont.)

ma g i

()

10 0

1 10

10 0

L oop G ain M ag ( dB )

ph a s e i

()

10 0

1 10

18 0

13 5

L oop G ain P h ase ( D eg r ee)

Layout Guidelines

Fig. 2. Bode plot of the loop

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