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MPQ4473GL Datasheet(PDF) 14 Page - Monolithic Power Systems

Part # MPQ4473GL
Description  High-Efficiency, Fast-Transient, 3.5A, 36V Synchronous, Step-Down Converter with AEC-Q100 Qualified
PDF  21 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPQ4473GL Datasheet(HTML) 14 Page - Monolithic Power Systems

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MPQ4473
–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER, AEC-Q100 QUALIFIED
MPQ4473 Rev. 1.01
www.MonolithicPower.com
14
5/24/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
Figure 7 shows an equivalent circuit in PWM
mode with the HS-FET OFF and without an
external ramp circuit. The ESR ripple dominates
the output ripple. The VFB downward slope is
calculated as follows:
REF
SLOPE1
ESR V
V
L

(7)
From equation 7, the VFB downward slope is
proportional to ESR/L. Theref
ore, it’s necessary
to know the minimum ESR value of the output
capacitors without an external ramp. Also, there
is an inductance limit: a smaller inductance leads
to
increased
stability.
Based
on
bench
experiments, keep VSLOPE1 around 15V/ms to
30V/ms.
In skip mode, the external ramp does not affect
the downward slope; the downward slope of the
VFB ripple remains the same with or without the
external ramp. Figure 8 shows an equivalent
circuit with the HS-FET OFF and the current
modulator regulating the LS-FET.
Figure 8: Simplified Circuit in Skip Mode
The downward slope of the VFB ripple is:

REF
SLOPE2
1
2
OUT
V
V
R
R
C
(8)
To keep the system stable during light loads,
avoid large VFB resistors. Also, keep the VSLOPE2
value around 0.4V/ms to 0.8mV/ms. Note that
IMOD is excluded from the equation because it
does not impact the system’s light-load stability.
Soft-Start (SS)
The MPQ4473 employs soft-start (SS) to ensure
smooth output during power-up. When the EN
pin
goes
HIGH,
an
internal-current
source
(8.5μA) charges the SS capacitor (CSS). The CSS
voltage takes over the REF voltage to the PWM
comparator. The output voltage smoothly ramps
up with VSS. Once VSS reaches the same level as
VREF, it continues ramping up while VREF takes
over the PWM comparator. At this point, soft-start
finishes and the MPQ4473 enters steady state.
CSS is then:
 
 
 
 
SS
SS
SS
REF
t
ms
I
A
C
nF
VV

(9)
If the output capacitors have large capacitance
values, avoid setting a short SS or risk hitting the
current limit during SS. Select a minimum value
of 4.7nF if the output capacitance value exceeds
330
μF.
Power Good (PGOOD)
The
MPQ4473
has
power-good
(PGOOD)
output. The PGOOD pin is the open drain of a
MOSFET. It connects to VCC (or a different
voltage source) through a resistor (e.g. 100k
Ω).
In the presence of an input voltage, the MOSFET
turns ON so that the PGOOD pin is pulled to
GND before SS is ready. After VFB reaches
90%xVREF, the PGOOD pin is pulled HIGH (after
a delay, typically 700
μs).
When the FB voltage drops to 85%xVREF, the
PGOOD pin is pulled LOW.
Over-Current Protection (OCP) and Short-
Circuit Protection (SCP)
The MPQ4473 has cycle-by-cycle over-current
limit control. The inductor current is monitored
during the ON state. Once the inductor current
exceeds the current limit, the HS-FET turns OFF.
Simultaneously, the OCP timer starts. The OCP
timer is set at 100
μs. Hitting the current limit
every cycle during the 100
μs time frame will
trigger hiccup SCP.
If
a
short
circuit
occurs,
the
MPQ4473
immediately will hit its current limit and VFB will
drop below 50%xVREF (0.815V). The device
considers this an output dead short and will
trigger hiccup SCP immediately.
Under-Voltage Protection (UVP)
The MPQ4473 monitors the output voltage
through the tap of a resistor divider to the FB pin.
This detects output under-voltage conditions.



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