ACT8847 datasheet(28/42 Pages) ACTIVE-SEMI

28 / 42 page

ACT8847

Rev 9, 27-June-17

Innovative PowerTM

- 28 -

www.active-semi.com

ActivePMUTM is a trademark of Active-Semi.

I2CTM is a trademark of NXP.

Table 3:

ACT8847 and S5PC210 Signal Interface

ACT8847

DIRECTION

SAMSUNG S5PC210

PWREN

XPWRRGTON

SCL

Xi2cSCL[0]

SDA

Xi2cSDA[0]

VSELR2

DVS_GPIO1

GPIO1/VSELR3

DVS_GPIO2

GPIO2/VSELR4

DVS_GPIO3

nRSTO

XnRESET

nIRQ

XEINT0

nPBSTAT

XEINT1

PWRHLD

XPSHOLD



: Typical connections shown, actual connections may vary.

nPBIN

ACT8847

Manual

Reset

Push-Button

nPBSTAT

Manual

Reset

Detect

Push-

Button

Detect

To CPU

INL2

VIO

50kΩ

Control Signals

Enable Inputs

The ACT8847 features a variety of control inputs,

which are used to enable and disable outputs

depending upon the desired mode of operation.

PWREN, PWRHLD are logic inputs, while nPBIN is

a unique, multi-function input.

nPBIN Multi-Function Input

The ACT8847 features the nPBIN multi-function

pin, which combines system enable/disable control

with a hardware reset function. Select either of the

two pin functions by asserting this pin, either

through a direct connection to GA, or through a

50kΩ resistor to GA, as shown in Figure 2.

Manual Reset Function

The second major function of the nPBIN input is to

provide a manual-reset input for the processor. To

manually-reset the processor, drive nPBIN directly

to GA through a low impedance (less than 2.5kΩ).

An internal timer detects the duration of the MR

event:

Short Press / Soft-Reset:

If the MR is asserted for less than 4s, ACT8847

commences a soft-reset operation where nRSTO

immediately asserts low, then remains asserted low

until the nPBIN input is de-asserted and the reset

time-out period expires. A status bit, SRSTAT[ ] , is

set after a soft-reset event. The SRSTAT[ ] bit is

automatically cleared to 0 after read. After Short

Press, set WDSREN[ ] to 1 about 1s after nRSTO

de-assert then clear WDSREN[ ]

for properly

shutdown sequence.

Long Press / Power-cycle:

If the MR is asserted for more than 4s, ACT8847

commences a power cycle routine in which case all

regulators are turned off and then turned back on. A

status bit, PCSTAT[ ], is set after the power cycle.

The PCSTAT[ ] bit is automatically cleared to 0 after

read.

nPBSTAT Output

nPBSTAT is an open-drain output that reflects the

state of the nPBIN input; nPBSTAT is asserted low

whenever nPBIN is asserted, and is high-Z

otherwise. This output is typically used as an

interrupt signal to the processor, to initiate a

software-programmable routine such as operating

mode selection or to open a menu. Connect

nPBSTAT to an appropriate supply voltage through

a 10kΩ or greater resistor.

Figure 2:

nPBIN Input

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